EEC - Japanese Clocking Scheme

Japanese Clocking Scheme

The JMOS family and the Sony 500 Series of integrated circuits used a 2-phase clocking scheme for their flip-flops.

They appear to be Master/Slave flip-flops with the clocks for the master and slave sections kept separate. In the diagrams these are referred to as:

ΦC = Capture Input (Master section clock)
ΦT = Transition Input (Slave section clock)

The state of the inputs is captured under control of the ΦC input while the Q outputs are updated to be in accordance with the captured state under control of the ΦT input. This permits a system design where data capture is done in accordance with the requirements of the logic during one clock phase while all outputs are changed synchronously by a second phase.

The ΦC and ΦT inputs are driven by 2 out-of-phase and non-overlapping pulse streams. This made it possible to avoid the use of AC-coupled or edge-triggerred flip-flops which was common amongst others at the time.

Disadvantages were the additional connection to each flip-flop and the requirement of a rather hefty driver for the toggle pulse.

I have never seen this clocking scheme in any North American SSI logic family (where the master and slave sections of M/S flip-flops respond to different edges of one clock signal).

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EEC

Aug 2000