**************************************************************************** * Sherwood/Draco Micro/CPU-100 * Some Technical Notes from Reverse Engineering * * 2012 Jun / bhilpert **************************************************************************** Channel Numbers --------------- A channel or frequency is represented in the software by a channel number. A channel number is an index from 1 to 212, representing 100KHz increments starting from 87.5 MHz. Only odd channel numbers are stored (1,3,5..D3), regardless of whether odd or even frequencies are desired. The current channel number is incremented or decremented by 2 as the dial is rotated. For even frequencies, 1 is added to the channel number at the time the frequency is actually being set in the code. hex dec frequency --- --- --------- 00 0 not valid 01 1 87.5 02 2 87.6 03 3 87.7 04 4 87.8 05 5 87.9 06 6 88.0 .. 10 16 89.0 1A 26 90.0 24 36 91.0 2E 46 92.0 38 56 93.0 42 66 94.0 4C 76 95.0 56 86 96.0 60 96 97.0 6A 106 98.0 74 116 99.0 7E 126 100.0 88 136 101.0 92 146 102.0 9C 156 103.0 A6 166 104.0 B0 176 105.0 BA 186 106.0 C4 196 107.0 .. CE 206 108.0 CF 207 108.1 D0 208 108.2 D1 209 108.3 D2 210 108.4 D3 211 108.5 D4 212 108.6 Setting the Frequency with the Phase-Locked-Loop ------------------------------------------------ To set the desired reception frequency F(RCV), a value must be calculated for the 12-bit binary PLL divider count. The PLL reference F is 12.5 KHz, the VCO is predivided by 8, thus a unit count in the 12-bit PLL divider represents 100 KHz, the desired channel increment. The VCO frequency will be the reception frequency plus the IF frequency of 10.7 MHz: F(VCO) = 12.5KHz * 8 * ( (87.5+10.7)*10 + (channel-1) ) The PLL division factor is then: PLL(N) = 982 + (channel-1) The PLL divider is a binary up counter rather than a down counter, consequently it needs to be loaded with the negative of the count. This is done in the hardware by loading the counter with the 1s-complement from the count latch. However, the 1s-complement will take an extra count before overflowing and restarting, so the value to be loaded into the programmable divider is 1 less: DividerCount = PLL(N) - 1 = 982 + (channel-1) - 1 = 980 + channel Examples: Channel: 1 126 211 212 DividerCount: 981 1106 1191 1192 PLL(N): 982 1107 1192 1193 F(VCO) MHz: 98.2 110.7 119.2 119.3 F(RCV) MHz: 87.5 100.0 108.5 108.6 Register Use: ------------- R0 xxxx PC at reset R1 xxxx PC at interrupt R2 040F pointer to temporary storage R3 xxxx PC for main routines R4 xxxx PC for subroutines R5 xx misc loop counters R6 delay counter R7 04xx R8 0400 ref to current frequency R9 0410 call-sign memory pointer, will vary RA 0405 pointer to flag for STORE button RB xx flag RC xx flag RD tmp in SetFreq RE tmp in SetFreq RF xx return flag from CallScan RAM Use: -------- 0410 to 04FF is memory for the call-signs, organised as a simple array of entries. Each entry is 5 bytes, the first being the channel number, the remainder the 4 characters of the call-sign for display. 0400 current channel number 01 preselect A channel number 02 preselect B channel number 03 preselect C channel number 04 preselect D channel number 05 flag for store button and preselects 06 - 07 - 08 - 09 - 0A - 0B BCD F display digits 1 & 0 (LSDs) 0C BCD F display digits 3 & 2 (MSDs) 0D linear LED dial index 0E PLL divider upper 4 bits 0F PLL divider lower 8 bits, misc tmp 0410 call-sign memory, entry 1, channel number 0411 " , 1st character 0412 " , 2nd character 0413 " , 3rd character 0414 " , 4th character 0415 call-sign memory, entry 2, channel number .. ..etc.. 04FF call-sign memory, entry 48, 4th character 0500 alpha display, 1st character 0501 alpha display, 2nd character 0502 alpha display, 3rd character 0503 alpha display, 4th character ****************************************************************************