Digital Signal Analyser
|Serial Number:||5480A: 852-00171
|IC date codes 1968::1971, mostly late-68::early-69|
|Date of Receipt:||~ 2003|
|State upon Receipt:||
CRT trace, signal can be displayed from inputs, but there seems to be a problem in processing.
See Log entry of 2022 Apr 25.
Boards are mostly of early series.
Labeled with sticker from B.C. Children's Hospital.
|Procedure:||Schematics manual obtained: 5480-90013, "Printed Jan 1971". Source: ebay. Schematics only, Theory of Op and system structure are in a separate manual.|
Board and Assembly complement:
|Symptoms:||Trace is bright, intensity control has no effect, eventually reduces to bright dot on left of CRT.|
|Analysis:||+50V supply is at +39V. +/-50V board set up in test jig with two 24VAC transformers. Oscillation on input & output lines during portion of 60Hz cycle. Sense transistor 2N3053 is being operated over Vce spec. Removed and tried with higher V transistor but still some oscillation.|
|Solution:||Original replaced, board reinstalled to measure actual load current. Now works, output is clean. May have been just bad edge connector contact. Current into CRT PS board measured at 78mA @ 47V.|
A1 (Display) compartment, boards and CRT area damp-wiped.
A2 compartment damp-wiped.
A3 (Accumulator/Address) compartment and boards damp-wiped. Boards towards rear have some mold/grime on lower portions. Some corrosion on traces and TI IC pins. Isoprop and damp-wiped.
A4 compartment and board damp-wiped.
A5 (PS) boards damp-wiped.
5486 case, frame and boards damp-wiped.
5487 case, frame and boards damp-wiped.
5480 case, frame damp-wiped, upper & lower covers washed.
|Date:||2022 Apr 06|
|Procedure:||Observation: Circuit of A3A2U3.6 noticed to have lower resistance (-probe GND) than other outputs of same IC, all having equivalent circuits (1 output, 3 inputs). Measured in test setup, HIGH level of U3.6 is 3.7V while others are 3.9V. Logic operation is fine.|
|Date:||2022 Apr 07|
|Procedure:||In operation, signal can be captured and displayed. Setup: SYNC LINE, MODE AVERAGE, SWEEP 10mS, SWEEP COUNT 1, CHANNEL 1 ON, 60 Hz to channel 1, DATA mode. Press CLEAR, START, DISPLAY.|
|Date:||2022 Apr 07|
|Symptoms:||Switching between INPUT vs DATA on 5487, INPUT was showing 'analog' version of signal, then digitized. When switched to DISPLAY mode, noisy unsynced 60Hz appears, looking like an open circuit.|
|Analysis:||Looks like part of signal path is not switching to INPUT but remaining in DATA. Presumably normal behaviour.|
|Date:||2022 Apr 07|
|Symptoms:||Vernier level adjust on channel 3 is loose.|
Plastic coupling broken. Glued.
Mounting bar for pots on channels 1 & 2 had been bent, apparently to correct for to-short spacers between switch body and pot mounting bar. Manufacturing flaw. Mounting bars straightened, washers added on all 4 channels to add space.
|Date:||2022 Apr 08|
|Procedure:||PRESET/NORMAL knob tab had been broken off (was style like the TOTALISER knob). Replaced with cylinder-style knob (note replacement has different set-screw drive-key and thread size than other knobs on unit).|
Examination of operating manual and schematics indicates rear-panel system-interconnect connectors J15::J18 provide sufficient functionality to test and exercise many aspects of the 5480.
Controller program and adapter hardware created.
|Date:||2022 Apr 25|
Conversion is not linear e.g. the slope of a triangle wave is not straight, instead having bursts of semi-random variation (pattern does appear to be same at same points in cycle).
Error bursts appear around vertical low-order bits, ~32.
Also, process termination by preset sweep count only works for 1 & 2 sweeps count.
During exercise tests with new controller, two faults noted:
shift-left of 1 in accumulator fails from 4th bit to 5th bit when 3rd bit is 1, and counting up results in random extra increments e.g. counting up 0x10000 from 0 results in 0x10018.
Board A3A3 (high-speed accumulator) removed for bench testing. FF AC3 will set and reset, but during shift-left the clock signal appears riding at low amplitude on the Q & nQ logic levels. U4 (FF AC3) failed with internal short of pins 8 & 9.
U4 74H72 replaced with 7472.
Speed questionable but seems to work.
Unit now appears to be working properly. The sweep-count preset failure would be explained in that this function uses memory locations above 1000, and thus relies on the accumulator for operation.
|Date:||2022 Jun 11|
|Procedure:||Wire to 86A13.H opened and 86A13.7 grounded to allow for simpler remote control. With these alterations only SVQ_SUB needs to be asserted to enable remote control and the AR0/1 address bits will not be altered during remote control.|
|Date:||2022 Jul 07|
|Symptoms:||Similar problem to that of Apr 25: coarse conversion around low-bits and sweep count preset only works for 1 & 2 count.|
Functioning of PREP state figured out and then examined.
Shifting and preset-limit-bit detection seems to be working correctly.
Controller shows sweep count in memory 1020:1023 is not incrementing properly: sweep count oscillates 1-2-3-2-3-2-3-2-3-etc.
Bit 2^0 counts properly but bit 2^1 sticks 1 without generating a carry.
U2.8 noted to have poor LOW level, ~ 1V.
Board A3A3 removed again for bench testing, with monostable mock-up to generate 100nS clock pulse. Signal on pins U2.8 and U2.9 observed to be the same (FF AC0). Pins are internally shorted, same fault as with U4 although symptoms are not exactly the same.
U2 74H72 replaced with 7472.
Unit again appears to be working properly.
|Date:||2022 Jul 10|
Observation: With controller, sweep count after calibrated average processes (fixed sweep count) appears to be half what would be expected.
7: 0x3FC: 0x000041 0x000041 0x000040 0x000040 4: 0x3FC: 0x000009 0x000008 0x000008 0x000008 3: 0x3FC: 0x000005 0x000004 0x000004 0x000004 2: 0x3FC: 0x000003 0x000002 0x000002 0x000002 1: 0x3FC: 0x000001 0x000001 0x000001 0x000001 0: 0x3FC: 0x800000 0x800000 0x800000 0x800000