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Altair 8800i Unit Configuration |
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(Configuration in photo may differ from text).
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Configured state of Unit 221806K (2024 Apr).
Configuration
Boards from right to left:
- CPU: MITS88-CPU, original MITS CPU board, 8080 at 2MHz.
- New front panel interface board.
Front-panel.RDY jumpered to S100.pRDY.
- ROM: Simple ROM board, 2K in one 2716 EPROM.
Base address=0xF000 (60K) & 0xF800 (62K); the 2K is overmapped into 4K of address space.
The programs in the ROM were assembled relative to base address 0xF800.
Note the base address for the board is the complement of the labeling on the
blue rotary address switch on the board, e.g. "0"=0xF000, "1"=0xE000, etc.
- RAM: 4K EconoRAM I, static RAM. Base address=0xB000 (44K).
- RAM: 4K EconoRAM I, static RAM. Base address=0x2000 (8K).
- RAM: 8K PSS RAM8, static RAM. Base address=0x0000 (0K).
- I/O: MITS-2SIO, dual serial port. IO ports 0x10::13. 9600 BPS.
- I/O: MITS-4PIO, quad parallel port. IO ports 0x30::3F.
Power Supply:
The primary side is configured for 12V buck for the +8 transformer and 24V buck for the +/-16.
This is suitable for a line supply of ~120VAC with the above board configuration.
The toggle switch on the rear panel controls the fan, not really needed in this configuration.
ROM Contents
The simple ROM board has several programs in the 2K EPROM which can be run from the front panel:
- 0xF800: AltMon monitor program, needs RS-232 terminal for console (9600 BPS, 8N1/2).
This monitor is based on the Vector Graphics monitor from the mid/late-1970s.
See altairclone for documentation & source.
The installed monitor is assembled for a 6820 UART (as on 2SIO board) at I/O Ports 0x10,11.
Also requires RAM for the stack going down from 0xC000, which is provided for by the 4K RAM board at 0xB000.
- 0xFC00: Blinky A - simple program that rotates a bit through the front panel data LEDs.
- 0xFC10: Blinky B - another blinkylight program.
- 0xFC70: Blinky Address - produces random display of blinkylights in the address and data LEDs.
Makes the machine look like like its busy doing something sophisticated.
Sense-switches (A8::15) will change the speed of display.
Lowest switch ON sets minimum time, further switches ON set range for longer times.
- 0xFCD0: A preloader for the initial loader for Altair BASIC 4.0/4K.
This is just to save the effort of the original requirement of toggling in the initial loader from the front panel.
Loading Altair BASIC
Versions of Altair BASIC Interpreters can be found at altairClone [ref].
- Required:
- Serial console with ability to download file, connected to Altair console port.
- BASIC 4.0 4K .tap file.
- Run the preloader in ROM (see above) from the front panel.
This copies the initial loader to base 0000 and halts.
- OR, toggle in the initial loader for the original experience.
- Set the sense switches (8::15) to 0.
Pressing RESET runs the initial loader from 0000.
The loader will wait for input from the console SIO (at ports 0x10,11).
- Feed the BASIC4.0-4K.tap file to the SIO line. At 9600 BPS, use 8N2 to provide extra time for processing incoming bytes.
- The console should eventually present "MEMORY SIZE?".
For the 8K+4K RAM board configuration, respond with "12288".
Note upper case entry is required for responses and BASIC keywords.
Loading BASIC Programs
BASIC programs can be loaded into the Altair over the console line by sending the program-source file to be entered as text by the BASIC interpreter.
The interpreter however, requires time after the end of a line to process it, before it can accept characters of the following line.
The time required increases with the complexity of the line.
Adding null-bytes after the EOL is one way of addressing this.
At 9600 BPS, 100 null bytes is generally adequate, but may need to be increased in some instances. At slower speeds, the number of null bytes may be proportionately less.
With SCOMM
Using SCOMM, the following sequence loads the BASIC interpreter and a BASIC program.
Red text is operator action.
The column indicates which is the primary machine performing the activity.
Step | ALTAIR | CONSOLE/HOST |
1. | | CMD> SCOMM -d /dev/tty{port} -s 9600 -b 82 -rdi8 -se off |
2. | Power-on and get machine into STOP state |
3. | Set Address switches = FCD0 |
4. | EXAMINE |
5. | RUN |
6. | ...preloader executes, at end all address LEDS light (HALT instruction)... |
7. | Set Sense switches (A8::15) = 0 |
8. | RESET |
9. | ...initial loader waits for file, some address LEDs dimly lit... |
10. | | ^A |
11. | | SCOMM> sf basic4K40.tap |
12. | ...interpreter loads, takes some time... |
13. | MEMORY SIZE? 12288 |
14. | TERMINAL WIDTH? 80 |
15. | SIN? Y |
16. | ...BASIC marquee prints... |
17. | OK |
18. | | ^A |
19. | | SCOMM> sfnl cr |
20. | | SCOMM> snln 100 |
21. | | SCOMM> sf {pgmSrc.bas} |
22. | ...program echoed during transfer... |
23. | ...ready for RUN, LIST, etc... |
At step 9, one may press STOP, and execute front panel operations to alter the initial loader if desired, for example to load a different version of BASIC.
Pressing RESET followed by RUN then restarts the initial loader.
Front-Panel Lock-up
It is possible for the Altair 8800 to get into an apparent lock-up state which will not exit with normal front-panel operations.
All address LEDs light up, pressing STOP is ineffectual and while RESET may briefly produce some blinking lights, it ends up back in the same state with all address LEDS lit.
This lock-up occurs if the CPU executes a HALT instruction promptly after reset.
Once HALTed, pressing STOP will not change the machine state from RUN to STOP (explained below),
while pressing RESET sends it around to HALT again - the machine is stuck in a RESET-HALT loop.
This situation can occur at power-on if the front-panel comes up in the RUN state and the CPU encounters a HALT instruction during its consequent ramble through arbitrary memory.
The simple method to exit this lock-up is:
- Press & hold both STOP and RESET.
- Release RESET while holding STOP.
- Release STOP.
The machine should now be in the STOP state and front-panel operations can be performed.
Explanation
The 8800 front-panel logic contains a RUN/STOP flip-flop controlled by the associated switch and going on to control a RDY (ready) line on the bus and thence to the CPU.
Setting this FF to the STOP state is mediated by pSYNC and DO5 - this is to ensure the machine stops at the beginning, and not the middle of, an instruction.
The HALT instruction stops the CPU in a machine cycle after the beginning of the instruction.
In the HALT state, the CPU does not assert pSYNC, so pressing STOP will not change the R/S FF state from RUN to STOP.
Asserting STOP while pressing RESET in the switch sequence above ensures that the R/S FF will be enabled to STOP
promptly at the beginning of the first instruction after release of RESET, before any chance of encountering a HALT instruction.