Today, the DSO (Digital Storage Oscilloscope) is ubiquitous in electronics labs and workshops, having supplanted the analog scope and surpassed the latter in capability. They are also amazing instruments if one has been used to using analog scopes. There were storage oscilloscopes prior to the DSO, relying on a special holding-beam type of CRT, but these were limited to what amounts to a screen capture and were far more expensive and less common than standard scopes.

DSOs emerged as replacements for the analog oscilloscope starting in the early 1970s. The Nicolet 1090 [ref] (circa 1973) is an example, explicitly referred to and promoted as a "Digital Storage Oscilloscope". Due to limits of speed and memory, these early instruments were certainly not capable of replacing the general purpose analog scope in all applications.

Earlier, in the 1960s, some instruments were developed for specialised applications, largely in nuclear instrumentation, such as Multi-Channel-Scalers, Pulse-Height Analysers, and Signal Averagers. A common aspect of these instruments is the use of digital electronics, processing, and memory. In totality they contained all the functional elements of the DSO:

Given the time, these elements were too limited in speed and capacity to produce a DSO that could replace a conventional oscilloscope. They can however, be seen as presaging the DSO. The instrument presented here - the HP5480 - could, within its limitations, function as a DSO.

The HP-5480A Digital Signal Analyser was introduced in early 1968. Quoting from its announcement [ref]:

Also known as a signal averager or enhancer, the 5480A Signal Analyzer recovers repetitive signals buried in noise by averaging out that noise. It's ideally suited for applications in medicine, biology, spectroscopy, physics and vibrations analysis, as well as electronics.
The 5480 also does Multi-Channel-Scaling, and time and frequency histograms. With some external pulse-amplitude-discriminators it could be a Pulse-Height Analyser. It appears to be an attempt by HP to address several small markets for specialised instruments by producing one multi-function instrument. The basic specifications of the 5480 are 9/7/5-bit A-D resolution, up to 100KHz A-D conversion rate, and 1024*24-bit memory. The display resolution is 1000 H * 1024 V.

The Northern Scientific NS-544 Digital Memory Oscilloscope [ref] is another example, also from the 1967-68 period. Basic specs for the NS-544 are 7-bit A-D resolution, 16KHz A-D conversion rate, and 1024*16-bit memory.

The 5480 was announced in HP's Spring 1968 "New Instruments" catalog, and is last listed in the 1973 catalog. A catalog entry from ~ 1970 indicates the price for the 5480 configuration shown here would be $6950+$1500+$1800+$300 = $10,550, which inflates to $78,200 in 2022. The unit here has a property label from the B.C. Children's Hospital, and a calibration sticker from Jan 1975. The 5480 listed weight is 76 lb (34.5 Kg).

The HP Journal articles linked below present some examples of use of the HP 5480, one of which was analysing signals from pulsars in the period shortly after their discovery.

Contents (this page):

Sub-pages:

References / External Links:


Operation

The 5480 implements 6 process functions, selected by the FUNCTION switch:

Average and Summation have some similarity, but otherwise these functions are quite distinct in what they do, essentially configuring the system into different instruments.


CALIBRATED AVERAGE

Input signals are averaged over a preset number of sweeps.

Select: FUNCTION=AVERAGE, PRE/NORM=PRESET.
[Operating Manual, Figure 3-7, pdf.50::51]


WEIGHTED AVERAGE

Input signals are averaged until manually stopped. SWEEP-COUNT is the weighting constant for sweeps. E.g.: With SWEEP-COUNT set to 5, once past 32 sweeps each new sweep will contribute 1/32 to the average. With SWEEP-COUNT set to 2, once past 4 sweeps each new sweep will contribute 1/4 to the average.

The averaging can be observed in action by varying an input signal during execution. The lower the SWEEP-COUNT setting, the faster the new signal will appear out of the old average, as individual sweeps makes a larger contribution to the cumulative average.

Select: FUNCTION=AVERAGE, PRE/NORM=NORMAL.
[Operating Manual, Figure 3-7, pdf.50::51]


SUMMATION

Each sweep adds to an accumulating total of all sweeps. The sum can quickly go 'offscale' of the display, the SENSITIVITY MULTIPLIER can be set to scale the result down by factors of 2^n.

[Operating Manual, Figure 3-8, pdf.52::53]


FREQUENCY HISTOGRAM


Frequency histogram test. A signal generator was adjusted from 100KHz to 1MHz while stopping briefly every 100KHz.

Presents an occurrence distribution of measured frequency. In contrast to the other functions, the horizontal axis for the histogram functions is not time.

The frequency of the input signal is measured, in the manner of a frequency counter, by counting input transitions for a selected gate time. The resultant count is then used as an address into memory, and that memory location incremented to indicate an occurrence of that frequency. Over many gate periods then, a histogram of the signal frequency is built.

For example, with the SWEEP RATE set at 100mS/cm, the gate time will be 1mS=100mS/100 (note 'sweep rate' is a misnomer here, the S-R switch is selecting the gate period). A 1MHz input signal will produce a count of 1000 in 1mS. Say, during the process, that 1MHz is 'seen' for 52 gate periods. At the end of the process, memory location 1000 would record 52, and the display would present a dot at height '52' vertically on the far right of the display (10/10ths or 10cm from the left). If 600KHz was seen for 101 gate periods, then a dot would present at height '101' at 6/10ths (6cm) from the left of the sweep.

The signal to be analysed is input on the TRIGGER input, not one of the channel inputs of the input module.

[Operating Manual, Figure 3-9, pdf.54]

Test Example:


PERIOD HISTOGRAM

Similar to the Frequency Histogram function but measuring period rather than frequency. The period of the input signal is measured, by counting a selected reference frequency for a gate time determined by the input. These period measurements are tallied into corresponding memory locations to build a histogram.


MCS (Multi-Channel Scaling)


Multi-Channel Scaling test. A signal generator manually stepped up from 2 KHz to 11KHz, then gradually reduced down to 3KHz.

Produces a plot of event counts across time. The horizontal axis is time, in accordance with the setting of SWEEP_RATE. The vertical axis is the count of events seen at the MCS input during that fractional step period of the sweep. As the step periods are all equal, the vertical axis is presenting frequency.

    STEP_PERIOD(t/step) = SWEEP_RATE(t/cm) * 1(cm) / 100(steps)

In practice, during the sweep, memory is stepped through one location at a time, at each step a count of input events occurring during that step period is recorded in the current location.

"Channel" here is nothing to do with the signal input channels, the "channels" are conceptually the step periods for which events are counted, akin to channel in the sense of time-division-multiplexing. The events are pulses input via the MCS input on the rear panel. The front-panel signal input(s) were not used here for some reason.

[Operating Manual, Figure 3-10, pdf.55]


Using the 5480A as a DSO


Capture of 4 channels of logic state. The sweep rate here is 10mS/cm.

It is possible to use the 5480A as a DSO, albeit limited to some low KHz of signal capture. The image to the right shows the 5480 acting - in essence - as a logic analyser, capturing 4 state-sequencing signals in a Canon 161 calculator as it executes a simple multiplication (2*25).

The idea of course, is to 'average' or 'sum' just one sweep:

Note: The TRIGGER input is 1M impedance at low voltage but has clamps at ~ 3V thru only 82 ohms, thus may affect an input signal over 3V. AC mode adds a 0.1 uF capacitor in series.


Technical / Implementation

The digital logic of the 5480 is implemented with TTL ICs, primarily 7400 and 74H00 series. Most of these ICs are SSI although a few 7490 MSI devices are present.

The block diagram to the right presents the functional internal structure and primary signal and data paths. There is no CPU, hard-wired logic executes the process sequences.

The accumulator may be considered the focal point of the design. The accumulator is a 24-bit register with several ALU functions incorporated: count-up, count-down, shift and rotate - both left and right, parallel-load, and clear. All arithmetic is performed by count and shift functions, there is no binary adder.

All digitised signal data goes through the accumulator, during both input capture and processing, and output recall.

The memory is magnetic core: functionally 1024 words by 24 bits. Physically, it is a stack of 6 planes with 4 bit-arrays per plane, wired in 3D 4-Wire form. A small state machine is dedicated to generating the read/write cycles for the core.

The signal input amplifiers are potted FET-input op-amp modules from Teledyne. The rest of the analog circuitry is entirely discrete, including some number of op-amps. This is a little curious as some op-amp ICs such as the µA709 and LM101 were available in that period.

The multiple signal channels are diode-switch multiplexed into a single sample-&-hold and A-D converter. The channels can be individually enabled or disabled. The memory is apportioned to enabled channels in full, halves or quarters. Thus, with a single channel enabled, that channel will have a horizontal (time) resolution of 1000 (1000 words of memory dedicated to it). With two channels enabled each channel gets 500 words, etc.

The A-D conversion provides up to 9-bit resolution, but is progressively reduced to 7 and 5 bits at the two fastest sweep rates:

D-A conversion provides 10-bit resolution on both the vertical and horizontal axes of the CRT display. The horizontal display is actually only 1000 pixels rather than 1024, thus across the 10cm of the CRT horizontal graticule, 100 pixels per cm. Some of the remaining 24 words of memory are used for variables in the process algorithms.

The much larger 24-bits of the accumulator and memory, relative to the A-D-A conversions, are provided both to allow a larger total in summation, and room for shifting for scaling and averaging. Note the vertical DAC takes its input from the high-order bits of the accumulator.


Photos


The left-side module is for process control logic, here the 5486A. The right-side module is signal input, here the 4-channel 5487A, containing input amplifiers, sample-&-hold, and ADC. There were alternatives for the input module: the 5485A 2-Channel Input and 5488A Correlator Input.

Rear panel with a plethora of connectors.

Top internal view. The edge connectors and wiring harnesses seen in the upper half of the photo are the memory module with core stack and core support circuitry.

The core memory module rotates up. The 1024*24-bit core stack is the square block. The long boards are X, Y & inhibit drivers, sense amps, and horizontal & vertical digital-to-analog converters. One of the smaller boards contains the 20MHz master clock.

Bottom-rear view. The compartment seen at upper-left holds boards implementing the 24-bit accumulator and 10-bit address registers. At lower-left is the bottom of the power supply.

Service Controller using an RPi host connected to the 5480. The controller allows various elements of the 5480 such as the accumulator and core memory to be exercised and tested manually via a remote program.

Service Controller connections to rear panel.

The Horizontal Digital-to-Analog Converter board. This DAC converts the digital memory address to analog to produce the horizontal sweep on the CRT. Another similar DAC converts the memory location contents to analog for the vertical position on the CRT.

The Analog-to-Digital Converter board for digitising the input signals. The ADC is a slope integrating type, with three selectable rates.

A typical logic board. The digital ICs in the model are 7400-series TTL. The 5480 was released in 1968, so would have been in design earlier. This was a little too early for much in the way of Medium Scale Integration so the ICs are mostly SSI.

High Voltage supplies for the CRT.