Manufacturer:MITS
Model:Altair 8800b
Serial Number:5401723K
Year of Manufacture:1977
Date of Receipt:2021 (for refurbishment)
Source:UVic
State upon Receipt: On front panel, one switch is broken, several are bent.
Grubby interior.
Power cord cut off.
Fan grill is missing.
Front panel interface board is missing.
No CPU or memory boards.

Date: 2021 Jun
Procedure: Unit state assessed.
Plans and new schematic drawn up for replacement front panel interface board.

Date: 2022 Aug
Procedure: Chassis dismantled, washed.

Date: 2022 Aug 21
Procedure: Power supply:
  • +8 wiring redone.
  • -18 transistor remounted.
  • Mains wiring and transformer primary redone.
  • IEC mains connector added instead of fixed power cord, at previous location of fuse holder. Existing hole above enlarged to accept fuse holder.
  • Fan switch added.
  • Fan grill was missing, new one cut from stock for replacement.
  • Power supply and chassis reassembled.

Date: 2022 Aug 25
Procedure: Bus board:
  • Dismantled and wiring removed.
  • Oddball edge connector removed from slot 9. Connector was not suitable for thick PB base due to short pins. Holes for this slot appear to have been enlarged, PC traces very narrow or broken around holes. Holes soldered over for continuity.
  • Cleaned and flux removed with 3-4 cycles of isoprop, toothbrush, warm water and dish detergent. Once flux was removed, numerous poor solder connections (mostly partial fill) observed - to be redone with new solder tip.
  • Pin 5.r fouled by solder blob at bottom, removed. Pin 10.26 bent on inner run, straightened. Pin 8.47 bent on outer runs, straightened somewhat but contact face to baord is not even, may be better to avoid slot 8.
  • Power supply wiring redone.

Date: 2022 Aug - Oct
Procedure: Front panel:
  • STOP/RUN broken, replaced
  • A15 significant bend down, straightened
  • A8,A9,RESET minor bend, straightened
  • Several other switches tweaked slightly for straightness
  • In removing the STOP/RUN switch, plate-through for the center pin pulled out. This hole is part of ground circuit continuity so conduction across sides must be ensured. 2 wire jumpers in other through holes added to connect the segments of ground, one near the switch, another at pads near L3/UFPZ1 which appear to have been intended for a jumper.
  • 4 tantalum caps replaced with electrolytics.
  • 5V regulator bypass R remounted on component side of board.
  • LED at D0 was oddball earlier replacement. Replaced with color/brightness match from surplus.
In isolation and 1702 removed, quiescent state current draw on logic +5 = 0.82 A.

Date: 2022 Oct 10
Procedure: Replacement Front Panel Interface board completed. In isolation, quiescent state current draw = 0.10 A.

Date: 2022 Oct 13
Procedure: Altair CPU board:
  • Quite grubby. Cleaned by damp wipe and brushing.
  • Clock mod redone, 2*470R and 47p cap replaced.
  • Crystal reseated with foam insulation.
  • Heat sink cleaned up, new grease, position adjusted.
  • Socket (two strips) for 8212 has deteriorating plastic (white powder). Replaced.
In isolation and 8080 removed, quiescent state current draw = 0.46 A.
Clock periods by scope observation: Φ1=130ns, Φ1-2=40ns, Φ2=230ns, Φ2-1=100ns.

Date: 2022 Oct 21
Procedure: Powered up with full front panel and CPU board minus 8080.
  • D2 LED not lit. Replaced with same as D0.
  • D6 LED slightly dimmer than others. Replaced with same as D0.

Date: 2022 Oct 23
Procedure: CPU interface fixes:
  • STSSTB:
  • FREADY:
RUN/STOP & Reset now work.

Date: 2022 Nov
Symptoms: Most front panel functions show screwy behavior.
Analysis: 1702 ROM read. Mostly 7F's with a few FF's and a few 0 bits. Erases to all 7F's.
Solution: 2716 programmed and adapter built to substitute for 1702.

Date: 2022 Nov
Symptoms: Front panel still showing screwy behaviour. Notably, Examine-Next usually but intermittently increments PC by 2.
Analysis: Looks like two instructions being executed rather than the one NOP. Scope shows two SYNC pulses being generated. Timing for front panel dropping ready (via UFPT1.8) is too late, nearing or entering Φ2. Consequence of long line of gates from UFPT1.10 to UFNs.7 (RDY).
Solution: STSSB substitute of Φ1 changed to ~Φ2 so reset of UFPM1.8 can start earlier.

Date: 2022 Nov 24
Symptoms: Memory board installed. Deposit & Examine results in FF displayed.
Analysis: 8800b displays bus DO rather than DI and requires DI to be enabled onto CPU data bus so mem data can make its way to DO. This is supposed to be accomplished by DIG1~, a signal particular to the 8800b, from the FP to the CPU board.
Solution: SSWI~ moved to be fed from DIG1~.
Deposit & Examine memory operations now functional.

Date: 2022 Nov
Symptoms: 3 memory boards from JRubin restored to function.
  • EconoRam I - full 4K functional.
  • EconoRam I - 2K functional, need chips for other 2K.
  • Thinker Toys SynchroFresh - reverse-engineered, 4K functional, 1 chip bad in other 4K.

Date: 2022 Dec
Procedure: Several pins deformed/bent on bus edge connectors (black) (counting from right):
  • 10.2,3,4,5,6,52,53,55,56
  • 12.2,52,53
  • 14.52,53
Some straightening performed.

Date: 2022 Dec 07
Procedure: Replacement 2107 IC received for Synchrofresh memory board (original ICs are Western Digital RM1701G-25 / dated 7613). Source ebay listing was Intel D2107C-2, label visible on received is faded Intel D2107C (-2 may have faded off).
Synchrofresh now 8K functional.

Date: 2022 Dec 10
Procedure: MITS 88-2SIO serial board restored. Serial Output Test and Serial Echo Test successfully executed.

Date: 2023 Jan
Procedure: Current measurements for Synchrofresh 8K. V+18 draw:
  • SF8K pulled: 237 mA
  • SF8K present, not selected: 338 mA
  • SF8K present, selected: 455+ mA
Subtracting:
  • SF8K V+18 not selected: 101 mA
  • SF8K V+18 selected: 218+ mA

Date: 2023 Mar
Procedure: Recreation 8800 CPU board assembled. Deviations from original:
  • Clock oscillator altered to use feedback bias on the inverters rather than fixed bias.
  • Timing resistor for Φ1 reduced to 10K rather than 13K, shortening Φ1 from ~ 120nS to ~ 100nS. With a 12K resistor, the Φ2 to Φ1 delay was ~ 65nS, below the 8080 spec minimum of 70nS. Clock periods are now ~ (nS):
    • Φ1ll = 100
    • Φ1i to Φ2i = 35
    • Φ2ll = 275
    • Φ2i to Φ1i = 90
  • Three 750Ω resistors used for each 8080 clock driver, rather than two 470Ω.
  • Dropping resistor for -5V regulator increased to 820Ω/0.5W from 220/2W. Zener used is a 1N751A. Electrolytic filter capacitor reduced to 3.3uF.
  • Dropping resistor for +12V regulator increased to 51Ω.
  • 74LS367 bus drivers used instead of 8T97's.
  • IC L is 74LS74 rather than 74L74. The L74 may actually not be fast enough to provide adequate HOLD/READY setup time for the 8080, depending on the length of Φ2.
  • POC circuit: 2N3904 installed, later 100n cap replaced with 330n after one EconoRAM-I board fails to init to un-protected state, presumably due to too-short POC period.

Date: 2023 Mar
Procedure: MITS88-4PIO board refurbished. Several PCB traces needed patching. Base port address set to 0x30. Simple walking-bit test shows the 32 data I/O pins for ICs J & K to be OK as outputs (ICs L & M not present).

Date: 2023 Apr
Procedure: DB25 connector for JAIR board console constructed. Jair board configured for slave mode (CPU disabled). Installed in 8800b, serial echo program toggled in, successful. Boots to monitor and CP/M, BASIC runs in CP/M, using 64K JAIR mem, after removing 3 early mem boards.

Date: 2023 Apr
Symptoms: JAIR upper 8K disabled so two EconoRAM-I boards can be installed for upper 8K. One EconoRAM-I board (board with mixed 2102s) fails to init to un-protected state (can't write to it), due to too-short POC period.
Solution: On CPU board, 100n cap for POC delay replaced with 330n. CP/M boots.

Date: 2023 Apr
Symptoms: EconoRAM-III board shows erratic failures using front panel. A byte can be deposited, but repeated Examines will sometimes recall the correct value and sometimes recall a value with some bits inverted.
Analysis: While running a single-byte read-memory loop program, memory data looks correct on scope. Using front-panel, memory data as observed with scope does invert sometimes across repeated Examines. This was while using the recreation-MITS88-CPU board. Switching back to the period-MITS88-CPU board, the problem goes away.
Solution: ??

Date: 2023 Apr
Symptoms: PSS RAM8 memory board received (ebay purchase). Cleaned up, installed.
Examining locations via front panel results in upper address lights for board address going out and deposit-examines do not work.
Analysis: Suspected to be some odd interaction between the board, CPU and front panel via pRDY. pRDY will be pulled high when board is enabled, which can conflict with front panel pulling pRDY low. Need to look at isolating use of pRDY by front panel.
Solution: Pin U9.11 bent out to disconnect output from S100.pRDY.
Board now tests OK with basic deposit-examine of bit patterns 55 & AA in locations in all 8 1K segments.

Date: 2024 Apr
Symptoms: PSS8 8K RAM board has stuck-1 bit in bit 0 for 32 bytes at 0C00::0C1F.
Analysis: Problem location is U18, segment-7 bit-0. U18 swapped with U11 (segment-0,bit-0), bad bit moves as expected.
Solution: Signetics 21L02N-3 replaced with Fairchild 2102LF (350ns) at U11.


  Unit Log | Unit Configuration
Altair 8800b 		bhilpert
2021 Jun