Prior to the development of semiconductor LSI memory, magnetic core was the prevalent form of read/write or RAM memory in computer systems. Read-Only-Memory (ROM) technologies were also developed to fill the lesser need for fixed memories. One of those technologies was woven-wire transformer ROM. The technology is characterised by the selective weaving of wires through transformer cores but it may be distinguished into two techniques: in this article they will be referred to as the pulse-transformer technique and the switching-core technique.

While both techniques can commonly be found referred to as "core rope" in recent times, the historical accuracy of applying the term to the pulse-transformer technique is not clear. The term seems to have originated with the switching-core technique around the late-1950s/early-1960s - the term and technique can readily be found in association in documentation from that period, the same cannot be said for the pulse-transformer technique. On the other hand, the term "core rope" comes from the appearance the many fine wires used take on as they are woven through and around cores, and can be perceived as applicable to both techniques.

IBM used an implementation of the pulse-transformer technique for the microcode store in some machines in the 1960s, which they referred to as "TROS" for Transformer Read-Only Store.

Note the cores in woven-wire ROMs do not perform the actual memory function, rather they function as the core of forms of transformers. The memory contents is represented by the selective weave of wires through and around the cores. This is in contrast to core RAM, where the magnetic state of the cores represents and stores the data. In core RAM there is one core per memory-bit, in woven-wire ROM multiple bits are associated with each core.

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Pulse-Transformer Technique

Figure 1

In this technique, a set of pulse-transformers is formed. The transformer cores are operated in the linear region with the standard principles of transformers and induction, however each transformer may have multiple primaries. There is one core per bit-position of a word, that is, a memory of 16-bit words would have 16 cores.

The binary address is decoded to 1-of-n to drive n address-location wires. These wires act as primaries of the transformers. Each address-location wire selectively weaves through or around the cores to represent the data for that location. As shown in Figure 1, the ability to control both ends of a wire can be used to advantage to simplify the decoder electronics. The diodes ensure current goes through only the one desired location wire and not through parallel paths formed by other location wires.

Each core has one secondary winding - the sense winding - from which the data for a bit-position of the words will be read.

In operation, the address is presented to the decoder. A strobe pulse enables a current pulse through the one selected address-location wire. For the cores which have this wire woven through them a pulse will be induced in their sense winding, those cores which the wire does not go through will not, the consequent pattern of bits is the read data word for that location.

The cores may be constructed from two halves such that they can be opened for access during the weaving process.

Example: The Microcode ROM of a Wang Calculator

The Wang 500, 600 and 700 series of calculators, from the late-1960s/early-1970s, utilised a substantial woven ROM of the pulse-transformer form for the microcode store. Shown and described here is the ROM from a Wang 520 calculator.

This is the entire ROM module, with address decoder, cores, and 'sense latches'. The module is 17 by 12 inches (see ruler in leftmost picture). This implements a 2048-word by 42-bit memory. As such, there are 42 cores, located in groups of 4 within the yellow plastic housings.

The picture on the left shows one side of the module, holding the address decoders and the sense electronics. TTL ICs along the right and bottom edges decode the binary address to 1-of-32 and 1-of-64. Most of the area is occupied by a matrix of 2048 diodes for isolation of the address-location wires. The ICs and circuitry along the top form the sense latches. NOR gates are formed into 42 one-bit SR latches. The set of latches is reset at the beginning of a read operation, sense pulses trigger the latches to the set state to capture the read data. The sense windings drive an input of the NOR gates through some passive components, distinct sense amplifiers are not needed. The ICs forming the sense latches are Signetics SP380A - quad NOR gates of some family of current-sourcing bipolar logic.

The middle picture presents the side with the cores and address-location wires. Bundles of location wires on the left leave the 1-of-32 decoder to weave their way through the cores, then come back to split out to the array of 2048 diodes, and thence to the 1-of-64 decoder.

In the rightmost picture, a group of four cores has been opened and the weave can be seen. The cores are split into two parts, the U's forming three sides are visible, the fourth sides are at the bottom of the plastic housings. The woven address-location wires are down around #42 gauge (0.002-0.003 inch). A dump of the ROM contents indicates that up to 1200 location wires go through a core. The individual leads coming out along the bottom are from the sense windings.


Switching-Core Technique

This technique is more complex than the pulse-transformer technique, both in construction and operation. The principles of "magnetic core logic" are employed: the type of core utilised is chosen for operation in the non-linear region and the magnetic state of the cores is switched during operation (see magnetic-core principles). Two organisational schemes have been identified as using this technique, one used in the ElectroLogica X1 computer circa 1957 [Ref. 8], and one used in the Apollo Guidance Computer (AGC) circa 1964. The AGC scheme is presented here.

Note: In the following discussions, a unit current is a current level sufficient to flip the magnetic state of a core when passed through the core. A half-current is a level such that two half-currents are required to flip the state.

Apollo Guidance Computer Switching-Core Scheme

Figure 2

A small version of the AGC switching-core scheme is described first to introduce the topology and concepts, followed by the larger and more complex arrangement of an actual version of the AGC fixed memory.

There is one core for each addressed location in the memory, that is, a memory of 4096 words would have 4096 cores. There are two non-uniform sets of wires woven through the cores. One weave implements a 1-of-n decoder for address decoding. The second weave represents the data contents. An additional wire - the SET/RESET wire - is threaded uniformly through all cores.

The address-decoding weave is implemented with pairs of wires referred to as inhibit wires. For each address bit there is an inhibit pair. One wire of a pair carries current when the corresponding address bit signal is 0, the other wire when the bit is 1. Each core is threaded by one or the other wire of each address-bit inhibit pair, woven in such a manner to implement a 0..n binary sequence. A given core is woven with the wires which carry current corresponding to the complement of their address. This may seem counter-intuitive but the function of these wires is to inhibit cores: only the core which is being addressed will not see any inhibit current.

For example, in Figure 2 - a simple system with 4 words of 3 bits each - the core at binary address 00 is woven with the two inhibit wires which carry current when their address bit signal is 1. This core will see no inhibit current only when all address bit signals are 0. All the other cores have at least one '1' bit in their address and so have at least one wire which carries inhibit current when an address bit signal is 0, and will see at least one unit of inhibit current when location 0 is addressed.

The data weave is a set of sense loops, one loop for each bit-position of a word. The sense loops selectively weave through or around the core at a given address location to encode the data for the word at that location.

In operation, the objective is to flip the magnetic state of the one addressed core, while inhibiting all the other cores from doing so, and sensing the pulses induced in the sense loops by the flip to obtain the data for the addressed location. Reading then, involves a sequence of actions:

  1. The address is presented to the drivers of the inhibit pairs, enabling current through the appropriate wires. All cores except one see at least one unit of current from the inhibit wires threaded through them. This current is sufficient to saturate those cores. The core with no inhibit current is the selected core, at the specified address.
  2. The SET/RESET wire is pulsed with a unit of current opposed to the inhibit currents. For the unselected cores the magnetic field of this current is of no effective influence as it is cancelled by that of the inhibit currents. The selected core however, sees a magnetic field sufficient to flip it's magnetic state to the set state.
  3. The sense amplifiers are enabled and the SET/RESET wire is pulsed with current of the opposite direction (same direction as the inhibit currents). The magnetic state of the selected core flips to the reset state. The flip induces current pulses in those sense loops which are woven through the core, generating pulses for the set bits of the data word at the addressed location.

While this technique is more complex and may be slower than the pulse-transformer technique due to the sequence of actions required for a read operation, implementing a 1-of-n binary decoder within the cores represented a considerable savings in electronics in the days of discrete and SSI logic.

Comment: [Ref. 3] refers to sensing the flip to the set state. Other documents indicate using the reset flip. While in theory either might be used, in practice the reset flip may be the more reliable. Under certain circumstances, such as the initial state of the memory after manufacture or after power failure, cores may already be in the set state when selected and no flip would occur to induce a sense pulse. In contrast, the flip of the selected core to the reset state is ensured.

Comment: [Ref. 2] discusses in more depth various technical issues such as noise minimisation in sensing.

Example: The Program ROM of the Apollo Guidance Computer

The Apollo Guidance Computer (AGC) is likely the best-known system to use a core-rope implementation. The AGC went through several iterations during its development and the core-rope program ROM similarly went through several configurations. One of the configurations will be examined here: the 12,288-word by 16-bit ROM of the AGC 4, the first version of the Block II AGC. While the principles are as described for the switching-core technique, the AGC design utilises some additional techniques of interest. The following description is largely a re-expression of information from [Ref. 3]. It would be helpful to examine the AGC engineering schematics, but, while there is a set of schematics available [Ref. 7], the drawing pages for the memories do not seem to be included.

Figure 3

The overall logical organisation of the ROM is shown in Figure 3.

The cores are arranged in ropes of 1024 cores each. 10 inhibit pairs (20 wires) provide the address-decoder weave as 2^10=1024. Although the memory words are 16 bits wide, each core has up to 64 sense wires woven through it, logically grouped as 4 sets of 16. A set of 16 sense loops is referred to as a strand. The cores may be said to be 'overmapped', with 4 memory locations each. A rope thus stores 4*1024=4096 words. 3 ropes produce the total program memory of 3*4096=12,288 words.

Physically, each rope is constructed from 4 modules of 256 cores each, referred to as quarter ropes.

While in principle a strand would weave through the 1024 cores of a rope, for reasons of noise tolerances a strand threads only 512 cores, so there are 8 strands per rope.

Addressing involves selection of the appropriate rope, the address-weave decoder inhibit pairs, and selection of the appropriate strand of sense loops to feed the sense amplifiers.

The AGC address signals and decoding involve a bank register and some special decoding rules on the high-order bits. For purposes here the addressing is simplified to a uniform binary address. From this perspective 14 signals (A0 to A13) form the binary address to the ROM. These select a memory location as follows:

Note that some address bits do double-duty: A11 selects both inhibit decoding and strand groups, A12 and A13 select a rope by controlling the inhibit pairs, the SET and RESET wires and the strands. This ensures that - during each read operation - only one core of the entire ROM is selected and switched (saving power), and only one strand is gated to the sense amplifiers (necessary for effective detection of sense pulses).

The SET/RESET wire is implemented as two distinct wires. While this means one more wire through the cores, it simplifies the driver construction. The SET and RESET wires are driven from opposite ends, current no longer has to be switched in both directions through the same wire, unidirectional rope selection drivers can enable both these wires along with the set of inhibit pairs.

Figure 4

The strand selection is accomplished directly with the sense loops, using diode analog-switching techniques. Despite a total of 3*2*4*16=384 sense loops only 16 sense amplifiers are required. The design of the sense switches is shown in Figure 4. Enabling the driver for a strand sends current through the two diodes connected to each loop of the strand, sending them into conduction. The two resistors on the differential sense bus are matched so the current splits evenly between them and equivalent voltages are developed across them. The sense amplifier sees a net zero differential voltage at its inputs. While the diodes are in conduction, a sense pulse generated in the loop will reduce the current through one of the diodes while increasing it in the other, unbalancing the voltages across the bus resistors. The sense amplifier now sees a net voltage at its inputs. Other diodes on the same sense bus are held in reverse-bias and appear essentially as open-circuits to the bus.

From the above description a given core may have up to 2*10+2+4*16=86 wires through it. The AGC ROM memory would eventually be doubled to 24,576 words and finally tripled to 36,864 words. Some writings suggest this was accomplished by doubling and tripling the number of sense loops through the cores, so cores would be woven with 8, then 12 words each.


References

  1. Examination and reverse engineering of a Wang 520 calculator control store module.
  2. The Rope Memory - A Permananet Storage Device, by P. Kuttner, Burroughs Corp., AFIPS Proceedings 1963. Good technical description of switching-core technique.
  3. R-393 Logical Description of the AGC, Hopkins,Alonso,Blair-Smith, MIT 1963. See Chapter 4 (pdf-pg86). Describes the "AGC 4", first version of the Block II implementation.
  4. R-416 The Apollo Guidance Computer, by Alonso & Hopkins, Aug 1963.
  5. Evolutionary Dead Ends, by Alonso, Sep 2004. Some comments on switching-core rope function.
  6. Annotations by Hugh Blair-Smith to "Digital Apollo", 2008. Some corrections and hints about the AGC ROM sizes.
  7. AGC Block II Schematics. Sadly seems to be missing the pages for the memories.
  8. Communications from Paul Koning describing the ElectroLogica X1 switching-core scheme, from the description in "Cursus constructie X1" ("Course on the construction of the X1") by B.J. Loopstra and C.S. Scholten, 1957.