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The IME 86S is one of the models in the first generation of electronic calculators. IME was an Italian manufacturer - Industria Macchine Elettroniche. The 86S is implemented with Ge discrete-component logic and core memory.
The core memory uses several less-common and novel techniques to simplify it considerably compared to more usual core implementations. Briefly, it's a 2-1/2D organisation with one of the axis of wires shared for address and sense, see the Theory of Operation for more detail.
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An example of the logic boards. This is board 3 containing the FKP, FEX, FEEN & FESH flag flip-flops. |
| 51409751 | |
| 1966 (sample transistor date codes 6551,6449) | |
| 2024 | |
| Remote assistance to J.Ongena. Physical repairs by J.O. | |
| Largely functional but hangs on square root and several other faults per repairs of 2024 Sep.
A small board labeled "Minus Logik" is present taped to the top of the card cage and wired to board 4. |
| 2024 Sep | |
| Several DP neon lamps flickering or not illuminating. | |
| Replaced. |
| 2024 Sep | |
| 6th Nixie from right ghosts numerals from other digits. | |
| Anode driver does not turn off, likely BC leakage. | |
| Anode driver replaced with MPSA92. |
| 2024 Sep | |
| Broken diode on board 3 at ΦPCL input to AND gate feeding 3.12Nv. | |
| Diode replaced with BAT46. |
| 2024 Sep | |
| Fractional digit entry with DP at 8 F-Ds enters new numeral at 10^12 digit. | |
| - With DP at 8 F-Ds, double pulse occurs on TC=ΦD with the DP entry and then goes away with numeral entry.
This suggests the problem arises during the pulse burst that aligns TC=DP.
During this alignment TC is counting down.
- The double pulses are at TC=8 & TC=12. - TC comparator gate with ΦDC input is supposed to assert when TC=8 (FTC8=1, FTC4=0, FTC2=0, FTC1=0) - Conjecture: with the 4~ diode open at gate, that input is 1, so the gate asserts early, when TC=12 (it thinks FTC4=0 even though it is 1), and TC alignment stops with TC=12 rather than TC=8. Diode measures open. | |
| Diode at 4~ input replaced with BAT46. |
| 2024 Sep | |
| Pressing square root key hangs the machine. | |
| QB signals are persistently active - machine is stuck in QB loop. F32 is stuck 1, so no 0-edge to terminate QB. Diode for (I8~=>SG~&SC3=>SK~) input-pair of F32 failed open-circuit. | |
| Diode replaced with BAT46. |
| 2024 Sep | |
| Operations to Memory IV produce incorrect results, results from square root are also often incorrect. | |
| Square root uses M-IV, so fault is consistent with M-IV problem. Bit-2 of M-IV is always 0. Traced to open BC junction of transistor T22.13. | |
| T22.13 replaced with 2N2907. |
| 2024 Sep | |
| Accessing M-n for use as an operand leaves the sign of M flipped. | |
| FSM stuck 1. Q~ base gets reset trigger pulse and Q responds by going 0, but state does not hold. | |
| FSM.Q~ replaced with 2N3906. FSM now holds states properly and will set and clear on NEG keypresses, but intended effect is not apparent. |
| 2024 Sep | |
| Exponentiation results incorrect. Exponent counter increases by 3, result is often for N+1, e.g. 14^2=>15^2. | |
| Inverter 15.10Nv drives GR4INC to increment the exponent count. If the AND gates driving 15.19Nv had an open input diode, increments would occur at additional steps where they shouldn't. Diode at QMC input failed open. | |
| Diode replaced with BAT46. |
| 2024 Sep | |
| Overflow occurs on multiplication if DP is at far right (no fractional digits). | |
| DP=15 when there are no fractional digits. This state is explicitly tested for when multiplying by the AND gate feeding 7.1PL. Diode for F32~ input failed open. | |
| Diode replaced with BAT46. |
| 2024 Sep | |
| For first minute or so after power-on, division (and square root) produces incorrect results. Fault became worse over a few weeks to near-constant. | |
| Incrementing of Z, common to both DV & SR, is functioning well.
However testing with n/9 to give same value in quotient digits,
the length of QB1 assertion where subtract-and-increment is performed is varies.
This suggests a problem around the FCS & GASUB area producing bad subtractions bad sign change indications
Scope shows GASUB signal from inverter 5.10Nd has weak 1-level that decays into the 0/1 transition region. | |
| T5.10 replaced with 2N3906.
Unit fully functional. |
| 2024 Oct | |
| Numeral entry does not work. | |
| Traced to the FEEN flip-flop. T3.10.BE open, BC shorted. | |
| T3.10 replaced with 2N3906.
Unit fully functional. |
| 2024 Oct | |
| Intermittently, bits do not set 1 in 4th LSD, 8th, 12th. Those digits often remain 0. Problem may go away a few minutes after warm up, then return after unit is off for some days. | |
| ΦDd which addresses those digits is weak going to 1. RC curve on rise to -V (1-edge), and sometimes low amplitude. Something is failing to pull it to -V or something is excessively loading it to GND. Driving signals for ΦDd gate (ΦDC.1 & ΦDC.2) look good. Pull-up R for gate OK. This leaves leaky diode(s) on the many inputs driven by ΦDd as possible culprits. | |
| Diode for one of the high-side core drivers on board 28 replaced wuth BAT46. ΦDd signal improved though still some curve on 1-edge. ΦDd gate-input diode for digit anode driver of 4th LSD (T28.1) shows variability with cold spray. Diode replaced with BAT46. ΦDd signal now consistent in shape with other ΦDm. |
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IME 86S
Calculators | Integrated Circuits | Displays | Simulations EEC |
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