Early Electronic Calculator Sony SOBAX 2500 Calculator

Manufacturer:  Sony Model:  SOBAX 2500 Year:  1970 Form:  Desktop Functions:  Basic four, accumulator, 7 user memories, rounding, square root, programmable Number of Digits:  15 Display Type:  NIX Display: Hitachi CD81 Logic Technology:  SSI Memory Technology:  DELAY-MS Diodes:  137 Transistors:  78 Principal ICs:  Sony 500 Series IC Complement: Sony 501 (138) Sony 502 (35) Sony 503 (23) Sony 504-3 (35) Sony 504-4 (15) Sony 504-5 (4) (250 total) Tech. Data Level:  2 Tech. Data Source:  RE Tech. Data Pages:  27+11+52 Tech. Data: Schematic, Schematic Appendix, Theory of Operation

This calculator is based on a small IC family proprietary to Sony. Unfortunately these ICs have a propensity to fail (see the notes about the ICs), making it difficult to keep these calculators functional.

The 2500 is user-programmable, with storage for up to 111 program steps. An interesting facility for program flow control is provided: a single instruction provides for conditional execution, skip forward, and looping. The looping capability simply enables execution to loop from the end of the program back to the beginning.

The downside of this minimal flow control control facility is any 'complex' program which might normally be constructed as multiple loops must be formulated as a state machine. The upside is it was trivial to implement in terms of hardware, while being none-the-less quite powerful. One might guess that someone involved in the design had been studying computation theory and Turing-completeness.

Notable technically for the use of a magnetostrictive delay line in longitudinal mode (in contrast to torsion mode), and for the delay-line sychronisation methodology: rather than using a crystal-controlled clock and a bit density low enough to cover variability in the delay-line latency, the design uses a Phase-Locked-Loop arrangement. A channel slice in the multiplexed delay-line is pumped with a fixed pattern from the timing system, the bitstream from this channel feeds a phase-comparator to be compared with the timing, the comparator output feeds a charge pump controlling the master clock frequency, that is, the master clock is the PLL VCO. The master clock frequency is thus tweaked to keep the timing in sync with the delay-line.

Most of the logic is contained on six printed circuit boards which plug into a backplane. A small amount of logic is on the backplane PCB. The boards slide into the card cage at an angle to reduce the overall height. The magnetostrictive delay line is in a metal box mounted to the rear-most logic board.	View underneath of the backplane. There are two versions of the backplane with minor differences. The power supply at the rear is best accessed by removing the aluminum card cage above.	Board A, display and digit-timing counter. The display shield has been removed here.
Board E, an example of one of the straight logic boards. Two bad ICs have been removed, awaiting replacements.	Board F (1-539-224-12), containing the master clock, delay-line support and synchronisation circuitry. The actual delay-line is mounted on the rear. A bad IC has been replaced with a module hacked up from discrete components.	Another version of board F (1-539-224-11). Minor differences in some component values, but the layout also subtly changed for some reason. A bad IC at 410 has been replaced with an IC with a failed gate input patched to an unused but good input.
Inside the magnetostrictive acoustic delay-line (ADL) housing. The actual delay-line is the coiled wire. The transducers are two tiny solenoids mounted with white silicon putty a little ways in from each end. The printed circuit board contains a two-transistor read pre-amp. These elements are mounted on a sub-chassis supported on rubber standoffs in the housing for shock and vibration isolation.	Close-up of the ADL transducers, the pulse-injection and -exit solenoids. The injection solenoid is upper left, the exit solenoid is near center. The delay line wire is 10 loops of ~ 110mm diameter. With an additional ~ 160mm from the ends, the total length of the line is:          10*pi*110mm + 160mm = 3620mm The delay is ~ 1600µS. The pulse velocity then is:       3620mm / 1600µS = 2.26Km/S = 8140Km/h The delay line holds:       16 registers * 16 digits/register * 4 bits/digit = 1024 bits Thus each bit occupies about:       3620mm / 1024 bits = 3.5mm/bit of length in the delay line. Contrast this with the 6.0mm of the Monroe 925.	Board extender for servicing, built from scrap bits.
Drive signal to the ADL write solenoid (ADL.1).	Output from the ADL after the two-stage amplifier inside the the ADL module (ADL.9), DC-coupled to show the DC bias.	Output at ADL.9 with AC-coupling to remove the DC bias.
ADL output at Tf1.	ADL output at Tf2.	ADL output at QF5 collector.
Reformed data from the ADL at TF11 (ADLRD).