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This calculator is based on a small IC family proprietary to Sony. Unfortunately these ICs have a propensity to fail (see the notes about the ICs), making it difficult to keep these calculators functional. I received two units and was originally able to restore both of them to functionality, but one has since been relegated to being a sacrificial unit for ICs.
Notable technically for the use of a magnetostrictive delay line in longitudinal mode, in contrast to the more usual torsion mode.
Also, a channel slice in the delay-line is filled with a fixed pattern at power-up.
The bitstream from this channel feeds a phase-comparator in a Phase-Locked-Loop arrangement with the master clock as VCO.
The master clock is thus tweaked to keep it in sync with temperature variation of the delay-line latency.
Most of the logic is contained on six printed circuit boards which plug into a backplane. A small amount of logic is on the backplane PCB. The boards slide into the card cage at an angle to reduce the overall height. The magnetostrictive delay line is in a metal box mounted to the rear-most logic board. |
View underneath of the backplane. There are two versions of the backplane with minor differences. The power supply at the rear is best accessed by removing the aluminum card cage above. |
Board B, an example of one of the logic boards. A repair involving two diodes had been made on this unit, to fix a bad gate input in an IC. |
Board F, the main memory board, with the magnetostrictive delay line mounted on the rear. |
Inside the magnetostrictive delay line housing. The actual delay line is the coil of wire. The transducers are two tiny solenoids mounted with white silicon putty a little ways in from each end. The printed circuit board contains a two-transistor read pre-amp.
The delay line wire is 10 loops of ~ 11 cm diameter.
With an additional ~ 16 cm around the ends, the total length of the line is:
The delay is ~ 1600 uS.
The pulse velocity then is:
The delay line holds:
Thus each bit occupies about:
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Board extender for servicing, built from scrap bits. |
| 620173 | |
| 1970 (transistors stamped with 0J, capacitor with 9D) | |
| Acoustic Delay Line marked with "Type: 21.2, Lot No.: 107.2, Serial No.: 06594".
Board F (Master Clock and Acoustic Delay Line) marked with 1-539-22-12. Front panel engraved with "UBC 29-2000 #7". | |
| Sep 1999 | |
| UBC SERF. | |
| Display active but numeral entry does not work properly. | |
| Board B need 504 IC and repair of decimal point issue.
Board E needs a 502 IC, a 504 IC and repair of M register issue (May 2014). At this point, this unit (3) is a sacrifical unit for ICs for unit 620175 (5). |
| Sep 1999 | |
| Cleaned extensively, including rebuilding of keyboard with new rubber bumpers. |
| Oct 1999 | |
| Original power connector replaced with IEC standard. Power lamp replaced. |
| Nov 1999 | |
| Entering a number and pressing an operation key would result in some numerals (1,2,3,5,8) changing to other numerals. Shifting the decimal point would sometimes reveal the correct numeral. | |
| Conjecture and an examination of the incorrect bit patterns suggested the zero-blanking
procedure was affecting more than zeroes. Further conjecturing that the zero-blanking
procedure involved a pass through the digits to decide where zero-blanking begins,
followed by a pass to convert blanked zeroes (0000) to unblanked zeroes (1000),
it was determined that the J counter was used to hold the digit position of the transition
between unblanked and blanked zeroes and was indeed sometimes incorrect.
The problem was then traced back to a flip-flop in IC B105 which was supposed to be detecting whether a digit is zero (the DDISZ register). Examination of it's output (pins 9,10) suggested that the K input (pin 7) was stuck high, resulting in the flip-flop alternating instead of latching the data from register D. The J counter thus received improper indication of whether a digit was zero. Certain non-zero digits then had their W bit set in the second pass. The signal on the K input was correct. An input stuck high would be consistent with an open input. | |
| IC B105 was removed in anticipation of replacement. Upon reinstallation in a socket the
problem was solved. Whether the problem resulted from a poor solder connection or a poor
internal connection in the IC which was corrected by heat is unknown.
(01 Dec 2000: Repair to Unit 620175 suggests a resolution to this unknown.)
Fully functional. |
| 26 Nov 2004 | |
| Numerals not being displayed. '0's are present at powerup until initialisation completes, key presses result in processing activity, and the CHANGE SIGN and M keys function, but no numerals show up in the display. |
| 19 Feb 2005 | |
| Zeroes appear at startup, but at end of power-on-reset display goes blank instead of showing "0.0...". CHS functions to turn on the negative lamp, and operations seem to be performed, but display remains blank. | |
| Swapping board F with board from other unit returns functionality. With original board, MSYNC pulses are present coming out of read amplifier but QF6/QF8 flip-flop does not toggle. TF10 is always low. PCB trace to IC F302-11 cut, QF6/QF8 now toggles. Capture input (F302-11) must be problem, holding line low. Measures as diode drop to ground. | |
| Heating IC pin F302-11 restores functionality.
Fully functional. |
| 21 Feb 2005 | |
| Some numerals do not display properly after an operation is performed. Pressing "1+" results in ".0000" instead of "1.000". Improper numerals: 1 to blank, 2 to ?, 3 to 5&0, 8 to 6. Problem goes away after some minutes of being powered on. Operations actually produce the correct value, just not displayed properly. | |
| Swapping board B with board from other unit returns functionality. | |
| Not resolved, wait for the problem to become more permanent and hence easier to trace. |
| 20 May 2006 | |
| Problem of 19 Feb 2005 has reappeared. |
| May 2014 | |
| Improper numerals problem of 21 Feb 2005. | |
| Swapping with board (5)B restores basic operation. |
| May 2014 | |
| Memory indicators 1, 4, 7 on, M-selection inoperative. | |
| Suspect logic around IC E115. |
| 620175 | |
| 1970 (ICs stamped with 0F) | |
| Acoustic Delay Line marked with "Type: 21.2, Lot No.: 102-1, Serial No.: 04586".
Board F (Master Clock and Acoustic Delay Line) marked with 1-539-22-11 (this board is slightly different than those marked 1-539-22-12). Front panel engraved with "UBC 29-2000 #4". | |
| 28 Nov 2000 | |
| UBC SERF. | |
| Display active but showing random flickering numerals. | |
| Fully functional (May 2014). |
| 29 Nov 2000 | |
| Cleaned extensively, including rebuilding of keyboard with new rubber bumpers. |
| 30 Nov 2000 | |
| Original power connector replaced with IEC standard. Power lamp replaced. |
| 30 Nov 2000 | |
| High voltage (NIXIE supply) adjusted down from 220V to 200V. The higher voltage results in the voltage rating of some capacitors being exceeded. |
| 30 Nov 2000 | |
| When first received the display flickered randomly between numerals but with the same numeral in all digits at any given instant. After cleaning and reassembly this problem seemed to have disappered. However it reoccurs infrequently (once per several hours of operation), coinciding with a clicking of the "READY relay". Powering off and on restores proper operation. | |
| The clicking of the relay suggests that the RDY signal is being lost temporarily.
This might lead to a loss of sync between the master clock and the Acoustic Delay Line,
perhaps as a result of improper data being injected into the sync channel of the delay line.
An attempt to force the problem by shorting the "ready delay" capacitor produces similar but not identical results. | |
| See repair of 10 Feb 2001 |
| 01 Dec 2000 | |
| Thousands separators not being dimmed. The 2500 produces a thousands separator by turning on the appropriately positioned decimal point indicators, but dimmed relative to the proper decimal point. The dimming was not working: the thousands separators were in the correct position but of the same intensity as the proper decimal point. | |
The dimming technique (reducing the duty cycle) had been identifed during the
reverse engineering of Unit 620173. The symptoms suggested the duty cycle reduction was
not occurring. The problem was traced to the Q counter capture-clock gate
(IC B206, output pin 6). The signals on the inputs (pins 7,8,9) were correct but the
output (pin 6) was not responding correctly. Specifically, it was not responding correctly
to the signal on pin 8. Isolation of all inputs to this gate and resistance testing with
positive test lead on +4V (pin 2) and negative lead on the inputs resulted in:
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| Heating of pin 8 for 10 to 20 seconds with a soldering iron resulted in the input
achieving "diode drop" continuity to pin 2. This solved the problem.
(02 Dec 2000: Temporarily as it turned out.)
This is essentially the same problem as occurred wth the K input to IC B105 on Unit 620173. |
| 02 Dec 2000 | |
| Thousands separators were again not being dimmed. | |
| Apparently the IC had reverted to it's old ways. Reheating of pin 8 failed to bring back continuity. | |
| A new input to the gate was created using two diodes to feed into one of the good inputs.
Specifically: pin 7 (a good input) and pin 8 (the bad input) were rolled out of their
holes in the PCB and the cathodes of two diodes inserted into these holes.
The anodes were both connected to pin 7.
Logically, this is equivalent to feeding one input of the existing NAND gate with a new 2-input AND gate. There was some question as to whether this technique would be successful as it adds an additional diode drop which must be overcome for switching to occur in a low logic supply (4V) environment. However, the same technique is used elsewhere in the machine (by design) to expand gates. It was successful. Fully functional. |
| 10 Feb 2001 | |
| Instability problem continued from 30 Nov 2000. | |
| 4V supply occasionally not present at startup. | |
| Variable resistor for 4V supply tweaked to clean contact between wiper and resistance.
Unit now seems to be stable: no problems over a 4 hour run.
Fully functional. |
| 08 Jan 2003 | |
| After being off for several days or more, unit does not power up immediately. Will come on after some seconds or if power switch is flicked on/off. | |
| -10V supply not present at power-up, taking 4V supply down with it. | |
| Slight crack in solder connections observed around pins of 2SD28 power transistors, resoldered.
Stable over 14 hour run.
Fully functional. |
| 22 Feb 2005 | |
| After power-on-reset, display flashes randomly. | |
| Speculation is that after being off for a long period of time the delay line needs to be magnetised via the capacitor discharge pulse that is sent through it at power-off. | |
| Turning the unit off and on several times restores functionality.
Fully functional. |
| May 2014 | |
| Display does not clear, several digits flickering between numerals while other digits are blanked. | |
| Swapping with board (3)A brings up a properly cleared display. |
| May 2014 | |
| No numeral entry, although display flickers with keypress, indicating the keypress is being seen by the logic. | |
| Swapping with board (3)E restores basic functionality. Problem traced to N register clock logic, TE4 indicates stuck high. IC (5)E303 bad. All pins appear open to V+ & GND. IC (5)E303 replaced with 502 from (3)E303. OK. |
| May 2014 | |
| Back to digits problem on board A. | |
| Scope obervation indicates K input at (5)A107.7 of digit counter is behaving as if it is stuck high, foreshortening the numeral cycle.
IC (5)A107 replaced with 504 from (3)E110. OK.
Fully functional. |
| Mar 2020 | |
| Function keys are not recognised. After entering a number and pressing a function key, digits for the 2nd number simply continue the first number. The press of the function key is seen by the logic in that the display flickers for processing. | |
| Swapping of boards B,C,D from (3) does not help. Problem likely on board E. |
| Oct 2024 | |
| Entry of odd numerals results in overflow, while even numerals are fine. | |
| Signal S18+19+1A+1B at input E407.8 is OK but input is behaving as if stuck high, so OVF gets set at tD15 imediately after the N regsiter is loaded. | |
| E407 has a spare input (pins 9,10 wired together) that can replace pin 8. Pins E407.8 & E407.9 rolled out of holes and 9 wired over to PCB pad of 8. |
| Oct 2024 | |
| Continuing from Mar 2020. | |
| W flag that indicates within-number-entry is not being cleared, it should be cleared at S11 after function completion. EXEC is being cleared early, after SM*SK flags, before S0A. SK is not being cleared because E403.6 does not go 0 even when all 4 inputs are 1. E403 removed and tested, both gates will not go properly 0. | |
| Replacement circuit module for 502 IC constructed & installed. |
| Nov 2024 | |
| Mains fuse blown in course of work from switch contact. Replaced. |
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Sony SOBAX 2500
Calculators | Integrated Circuits | Displays | Simulations EEC |
bhilpert |
