The MPSI is a new (2014) plug-in I/O interface for the HP-9830 that provides for input and output to an external computer (referred to here as the host) over a simple clocked serial line. The MPSI implements 3 devices - that is, it responds to 3 select-codes from the 9830 - in one plug-in module:

1. A General-Mode I/O device optionally enabled on select-code #15. This allows the external host to function as a 9866 printer simulator, allowing print output from the 9830 to be displayed and captured on the host.
2. A General-Mode I/O device on a jumper-configurable select-code. This allows:
   • The external host to function as a paper-tape reader simulator, allowing BASIC source files to be loaded into the 9830 via the PTAPE# command.
   • The external host to function as a secondary printer, accessed via LIST#, WRITE(#).
   • Arbitrary data I/O with the 9830.
3. A Fast-Mode device on another jumper-configurable select-code. This allows the host to appear to the 9830 as an external 9865 tape-drive, the 9830 can perform cassette-tape read and write operations (e.g. LOAD#,STORE#) on tape image files located on the host. In essence, the host functions as a file server for the 9830.

The data link between the MPSI and the host is a straight-forward clocked serial line, similar to an SIO interface, involving 5 wires including ground, at TTL or 3.3V signal levels. It is not RS-232 async, the DB-25 connector visible in the photo was used merely because such connectors are abundant in surplus today. The design intention was to keep the hardware requirements (cabling, buffers, signals) to a minimum. The link is expected to be quite short, it is not intended as a medium or long distance communication link.

Contents (this page): Applications The External Host Construction Technical Description

Resources: MPSI Schematic (PDF) Support Programs Source (pgm9830.tgz)

Applications

• MPSI Server: A server program which simultaneously simulates 3 devices: a 9866 printer, a paper-tape reader, and a 9865 tape-drive.
• Tape Controller: A tape-drive control program. Operating in conjunction with a relay program downloaded into the 9830, this program allows tape images to be read from and written to cassette tapes in the 9830 internal tape-drive.

  The relay program is a binary program contained in the Machine Binary-Block, and can be downloaded into the 9830 from the host using the MPSI Server program.

Both programs are written in C. See the Resource links above.

The External Host

The paper tape and printing functions should function down to very slow clocking rates. The General-Mode I/O protocol HP used for these functions is fully ack'd and there are no response latency limitations. Python server programs are adequate here.

The tape-drive functions need clocking of the MPSI in the 1 MHz range and response latency in the tens-of-uS range. The RPi has been competent for the task even when manipulating the GPIO pins from C code running in userland, as long as there aren't any other tasks distracting the CPU/OS.

Construction

The second unit was built on a proto-board with edge connector. The board was trimmed to fit into an original HP interface housing. In this instance the ICs face down, just as they do in original HP interfaces.

See the schematic (PDF).

(Unit #2 bottom view).

Technical Description

The I/O bus of the 9830 involves over 30 signals. The MPSI reduces the many signals of the 9830 bus to a clocked serial interface of just 4 signals (SDI/data-in, SDO/data-out, SCP/clock, CTL/control) for communication with the external host. The serialisation is implemented with two 16-bit registers in the MPSI:

• the MRR (MPSI Receiving Register) receives output from the 9830 for transmission to the host,
• the MSR (MPSI Sending Register) with which the host sends input to the 9830.

HOST-TO-MPSI SIGNALS:

• SDO: Serial Data Out. 16-bit sequence of status and data to shift into the MSR. The bits, in first-to-last order, are:

  0	DI0	bus Data-Input-0
  1	DI1	bus Data-Input-1.
  2	DI2	bus Data-Input-2.
  3	DI3	bus Data-Input-3.
  4	DI4	bus Data-Input-4.
  5	DI5	bus Data-Input-5.
  6	DI6	bus Data-Input-6.
  7	DI7	bus Data-Input-7.
  8	-	not used, see ACK bit.
  9	SI1	bus Status-Input-1.
  10	SI2	bus Status-Input-2.
  11	SI3	bus Status-Input-3.
  12	-	not used.
  13	ACK	General-Mode ACK flag, will determine Status-Input-0 on +edge of CTL.
  14	CFI	CFI (Channel-Flag-Input) flag, will determine bus CFI on +edge of CTL.
  15	SSI	SSI (Single-Service-Input) flag, will determine bus SSI on +edge of CTL.

• SCP: Serial Clock, Positive edge. Clock for both SDI and SDO.
• CTL: Control. This signal controls loading of the 3 flags from the MSR and loading of the MRR from the output bus. In typical operation, the controller will hold CTL high, and take it low during the transfer of data between the MPSI and the host.

  When CTL=1 the MRR is able to receive requests and output from the 9830. An I/O request from the 9830 asserts the bus CEO (Control-Enable-Output) signal (nCEO=0). When CEO is asserted (-edge of nCEO) the MRR is loaded with the state of the 9830 output bus. When CTL=0 this loading is inhibited. For some Fast-Mode operations which do not require acknowledgement, the MPSI and host may miss an operation from the 9830 if the host does not respond quickly enough to the request from the 9830. Inhibiting the load ensures a subsequent CEO assertion will not corrupt the MRR contents while the host is clocking the MRR.

  The +edge of CTL loads the 3 flags in the MPSI (ACK,CFI,SSI) with the corresponding values of MSR bits 13,14,15. The flag flip-flops are present so the other status and data bus inputs from the MSR to the 9830 can be set before indicating their viability to the 9830.

These are LS-TTL inputs to the MPSI with pull-ups and clamps. They are safe for, and can generally be driven by, 3.3V outputs.

MPSI-TO-HOST SIGNALS:

• SDI3: Serial Data In. 16 bit sequence of status and data to shift out of the MRR. The bits, in first-to-last order, are:

  0	REQST	Request. 1 indicates the 9830 has initiated an I/O operation on one of the 3 MPSI select-codes. This is effectively a latched indication of the device-enable signal. This bit returns to 0 after a full 16-bit clocking of the MRR.
  1	TP	Tape-Device. 1 indicates the initiated I/O operation was on the configured TP select-code.
  2	GP	General-Purpose. 1 indicates the initiated I/O operation was on the configured GP select-code.
  3	PR	Printer. 1 indicates the initiated I/O operation was on select-code #15.
  4	nSO3	inverted bus Status-Output-3. For General-Mode this is the direction bit, 1=output, 0=input.
  5	nSO2	inverted bus Status-Output-2.
  6	nSO1	inverted bus Status-Output-1.
  7	nSO0	inverted bus Status-Output-0.
  8	nDO7	inverted bus Data-Output-7.
  9	nDO6	inverted bus Data-Output-6.
  10	nDO5	inverted bus Data-Output-5.
  11	nDO4	inverted bus Data-Output-4.
  12	nDO3	inverted bus Data-Output-3.
  13	nDO2	inverted bus Data-Output-2.
  14	nDO1	inverted bus Data-Output-1.
  15	nDO0	inverted bus Data-Output-0.

  SDI3 is a 3.3V-safe signal.

• nSDI: inverted TTL-level version of SDI.

Typically, the host will monitor the SDI signal, watching for it to be asserted. Because REQST is the first bit in the MRR, its state is normally present on the SDI line. When it is asserted the 9830 has initiated an I/O operation. The host takes CTL low to hold the contents of the MRR and clocks the MRR contents over to the host to obtain the operation data. At the end of the 16-bit clocking, REQST - and hence the SDI line - is deasserted.

THEORY OF OPERATION:

Note that the MPSI PR and GP devices both operate in General-Mode, while the TP device uses Fast-Mode.

• 1-of-10 decoder U1 decodes Code-Outputs 0,1,2,3 from the 9830 to produce the 3 device-select signals nTP, nGP, and nPR. Inverter U15a allows SC #15 to appear as one of the decoded outputs.
• U14c, U13d and U15f combine the 3 device-selects to produce a single device-select (DEV_SELECT). U13d is logically functioning as just an OR gate.
• Once a device is selected, the 9830 may initiate an operation by asserting CEO (nCEO=0). U15e and U14b produce the device-enable signal (DEV_ENB) by combining DEV_SELECT and nCEO.
• U2 and U3 form the 16-bit MRR shift register. When a device is enabled, monostable U12 is triggerred through D-FF U11b to load the MRR. The monostable is necessary because the 9830 will leave CEO asserted for Fast-Mode I/O interfaces (e.g. tape drives), a pulse is needed at the beginning of the assertion so the MRR parallel load does not remain asserted. D-FF U11b inhibits the triggerring of the load pulse when CTL is held low by the host. The first bit of the MRR (U3.D7) is held low to form the REQST bit, this corresponds with U2.DS being held to the inverse - high. U3.D4,5,6 receive the 3 device-selects so the host may distinguish the selected device. The other MRR inputs receive data directly from the 9830 status & data bus outputs.
• U4 and U5 form the 16-bit MSR shift register. U5.Q7 does not form the SI0 signal directly, in contrast to SI1-3, because SI0 is the ACK bit for General-Mode devices and must be double-bufferred via the ACK Flag FF U11a. This is so the MSR status and data bits can be updated and stabilised before indicating ready to the 9830.
• U11a forms the ACK flag for General-Mode devices. General-Mode devices clear the ACK flag when an operation is initiated (device enabled). It is then up to the device (host) to set the flag when ready. U9b inhibits operations on the TP device from clearing this flag. The host should nonetheless ensure the flag is set in-between operations on the General-Mode devices so that the tape device will appear as available (SI0=1) to the 9830.
• CFI (Channel-Flag-Input) Flag FF U10a is acknowledge/ready for Fast-Mode devices. The same logic of double-buffering the ACK flag applies to the CFI Flag. The CFI Flag is cleared when the device is de-enabled, this is normally done in feedback as CFI deasserts CEO in the 9830, which de-enables the device.
• U6, U7, U8 & U9 are open-collector gates to gate the MSR and flags onto the 9830 input bus. The gating policy for putting signals on the input bus differs slightly for General-Mode and Fast-Mode devices. U13b & U13c distinguish various signals for General-Mode and Fast-Mode operations.
• U13b determines the input-bus gating for the status lines. General-Mode devices present the status when the device is selected, Fast-Mode devices do so when the device is selected but not enabled.
• U13c determines the input-bus gating for the data lines. General-Mode devices present the data when the device is selected and service (interrupt) is inhibited, Fast-Mode devices do so when the device is enabled.

  (!!!NOTE: the gating policy has been implemented to mimic equivalent HP-designed devices. It may be possible to simplify this logic as the firmware may in fact not require some of these mode distinctions.)

• U10b forms the interrupt (Single-Service Input) flag. U9c places the interrupt on a configured DI/SI line so the 9830 can determine which device is interrupting. This is not done when service is inhibited via Service Inhibit (nSIH=0), so as not to conflict with data being put on the bus. The interrupt flag is cleared when the processor enables the device. The R & C on U14d ensure the interrupt flag is cleared at power-on.