HP 21xx
Series
Fairchild CTµL Integrated Circuits  

Fairchild CTµL (Complementary Transistor MicroLogic) was one of the first IC logic families, dating from the mid-1960s, and is a form of non-saturating, current-mode logic, similar to ECL.

To quote from the Fairchild 1966 catalog:

Fairchild Complementary Transistor Micrologic integrated circuits were designed for very high-speed, low cost commercial systems applications. The logic form is AND-OR-NOT. All circuits have provisions for output OR ties.

ITT second-sourced some of these ICs, based on the observation of some ICs stamped with "ITT" on boards in an HP 2116C.

Known Devices:

CTµL Integrated Circuits & Cross Reference
HP Fairchild F SL Function Refs
1820-0186 ? ? dual 2-in AND, dual resistors B2,2100
1820-0187 ? ? dual 2-in NOR, dual resistors B2,2100
1820-0482 ? ? binary to 1-of-8 decoder 2100
1820-0485 ? ? hex level restorer (2-in AND, quint 1-in) 2100
1820-0952 9952 SL3455 dual 2-in NOR F66,B2,2100
1820-0953 9953 SL3456 dual 2-in AND, 3-in AND F66,B2,2100
1820-0954 9954 ? dual 4-in AND F66,B2,2100
1820-0955 9955 ? 8-in AND F66,B2,2100
1820-0956 9956 SL3459 dual 2-in AND Buffer F66,B2,2100
1820-0957 9957 ? MS FF F66,B2,2100
1820-0964 9964 ? dual 3-in AND, 1-in gate, OR'able F66,B2,2100
1820-0965 9965 ? quad 1-in gate, OR'able F66,B2,2100
1820-0966 9966 ? quad 2-in AND, 2 outputs ORed F66,B2,2100
1820-0967 9967 ? JK FF F66,B2,2100
1820-0968 9968 ? dual Latch F66,B2,2100
1820-0971 9971 SL3467 quad 2-in AND, outputs ORed in 2 pairs F66,B2,2100
1820-0972 ? ? dual 2-in NOR, dual resistors 2100
1820-0973 ? ? dual 2-in AND, 3-in AND 2100
1820-0974 ? ? dual 2-in AND, dual resistors 2100
1820-0975 ? ? JK FF (similar to -0967) 2100

Source of Data, Key to Refs:

Period: Mid 1960s to early 1970s. The earliest direct reference is a Fairchild catalog from 1966. The HP 2116A was being designed at least as early as 1965. Additional devices show up in the HP 2100A, which was released in 1971.

Supply Voltages: Vcc = +4.5 V ±10%, Vee = -2V ±10%.

Technology: The diagram presents the basic schematic of CTµL AND and NOR gates. These are taken from the Fairchild 1966 catalog. Delay time is 3 nS for AND gates of this form, 9 nS for NOR gates.

 

Logic: Gate symbols are presented in accordance with

Packaging: Standard 14-pin DIP with some later devices in 16-pin DIP.

Note: IC packages as viewed from above.




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HP 21xx Series
bhilpert
Jan 2006