These pages attempt to present a technical overview and some reference material for the HP21xx series of processors. The focus here is on the technical aspects of the series, and more so for the early machines of the series. More comprehensive writeups of the development history are presented at sites listed below.
Disclaimer & Limitations: Before receiving an HP 2116C system in 2003, my experience with HP 21xx series computers was limited to passing by an under-utilised HP 21MX system in a university machine room in the early 1980s. (Under-utilised meaning it was from some defunct project and was rarely, if ever, powered up for the years I saw it.) Following is what information I have gleaned about the series from various sources, and from my experience with rejuvenating the 2116C. There is some deduction, some presumption (and the occasional opinion) involved.
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Early Models: The first processor of the series - the 2116A - was introduced in 1966. Over the next couple of years the 2114A and 2115A were introduced, sharing the same architecture and instruction set but with reductions in speed, expansion capabilities and size/weight.
The 2116/5/4 models differ mainly in the following:
A few revisions of these models were released, culminating with the 2116C in 1970. The 2116A/B/C models differ primarily in the maximum amount of memory which can be installed in the main cabinet.
Various hardware options could be obtained to provide extended arithmetic instructions, DMA, memory parity checking, and memory protection. Numerous types of I/O interfaces were available, as well as several pieces of expansion equipment:
The early models were contempories of the DEC PDP-8 in the mid-late-60s and competed with them in the marketplace. In contrast to DEC, which moved on to a new architecture in the early 1970s with the PDP-11, HP perpetuated the 2100 architecture through the 1970s and later 21xx models competed with the PDP-11s.
2100 Models: Reductions in the size of the memory modules over the course of the 2116A to the 2116C left a lot of empty space in the cabinet of the 2116C. This, together with replacement of the linear power supplies of the early models with a switching-mode supply, made it possible to produce a machine of similar or better capability than the 2116C in a cabinet nearer the size of the 2114. The early models were thus all superseded by the HP 2100A/S models in 1971.
The 2100 models also introduced proper micro-programming to the architecture, which contributed to extending the viability of the architecture into the future.
The 2155A I/O Extender was available to provide additional I/O slots. [ref: 12930 (pg. 2-1) interface manual.]
Around this time the architecture of the 21xx Series would also be adopted to form the basis of HP's early microprocessor-based desktop computers such as the 9830, 9825, etc.
MX-M & -E Series: In 1974 the 2100s were superseded by the MX series, the primary change being the replacement of core memory with LSI, based initially around 4 KBit chips. In 1975 another group of models providing improved performance were added to the product line. These standard and improved groups would be referred to as the M and E (Enhanced?) series.
1000-M, -E & -F Series: As near as I can figure the HP1000 name replaced the MX name, models were relabelled such that the suffix letter previously indicating the version now indicated the series (e.g. 2108B --> 2108M), and the F (Fast?) series models introduced.
The early models are based primarily on Fairchild CTµL small-scale integrated circuits.
CTµL (Complementary Transistor MicroLogic) was one of the first IC logic families, dating from the mid-1960s.
Supply voltages for the logic are
TTL ICs, and perhaps some DTL, also show up on many of the I/O interface boards and some other boards for these early models, running (marginally) off the 4.5V supply. Such boards may have a combination of CTµL and TTL ICs on them.
The 2100 models use a mixture of TTL and CTµL.
I don't have data but I suspect the 21MX and later models went to all or mostly TTL, as CTµL was obsolete by the mid-70s and TTL had improved in popularity, performance (Schottky and Low-power Schottky devices) and functionality (more MSI devices).
The exception to this was around the I/O bus, which retained the logic levels from the CTµL era for the sake of compatibility with existing I/O interfaces.
This would be something of an annoying legacy for the remainder of the series history, necessitating a
There are two 16-bit general-purpose registers (A and B), a 15-bit program counter, a 1-bit overflow flag and a 1-bit extend flag. Words in memory are 16-bits, addressing range is 32,768 words (the 16th bit in an address is used to indicate indirection).
The basic data format is 16-bit two's-complement integer. The overflow bit indicates overflow of the two's-complement (signed) interpretation of an accumulator. The extend bit indicates carry from 2^15 and so can be used for implementing multiple precision arithmetic, and is used in extended bit rotations.
When addressing memory from instructions, the address range is viewed in terms of pages of 1024 words. An instruction which references memory can directly reference locations in the base page (starting at 0) or the current page (the page in which the instruction is located). To get around this limitation, indirect addressing can be used.
Certain groups of what are referred to as micro-instructions can be combined into one word. While presumably a direct result of the hardware logic structure poking through to the instruction encoding this is not really micro-programming in the more proper sense of the term. See the Programming Reference for more about the instruction set.
I/O is accomplished by controlling channels, identified by select codes. A channel is physically implemented by an interface PCA (printed-circuit assembly) plugged into a slot on the processor I/O bus. The interface PCA is connected by a cable to the external device. Channels are controlled via I/O instructions, they are not memory-mapped. Each channel supports a control bit, a flag bit, and one or more registers. In general, the control bit is manipulated by the program to indicate to the device the start of an operation, the flag bit is used by the device to indicate to the program the completion of an operation, and the register(s) carry device-specific commands, status and data.
A few channels and memory locations are reserved for special purposes. See the Programming Reference.
Vectored interrupt handling is a standard provision of the processors. See the Programming Reference.
The M-register (memory address) and T-register (memory data transfer), while present in the hardware and on the front panel of some models, are not directly referenced by software.
The programming architecture and instruction set are fairly typical for smaller processors at the time of the original design (circa 1965), but just a few years later (by say 1970) the writing was on the wall for this architecture. By today's standards one can see various anomalies:
The architecture of the 21xx series also can be likened to a 16-bit version of the PDP-8 with two accumulators.
Anyone familiar with the PDP-8 processor will see a good deal of similarity between the two instruction sets.
(Note: the HP 3000 Management Systems use a different processor/architecture.)
| I/O Interfaces
| Programming Ref
| 2116C Refurb
HP 21xx Series