HP 21xx
Programming Reference  

Instruction Set Quick Reference

This reference covers the base instruction set applicable to processors up to and including the 2100A. The extended instruction set (a hardware option) and the additions of later processors are not covered.

The instruction set is broadly divided into 4 groups. The instructions documented here occupy a maximum of 1 word. In the Shift-Rotate Group and Alter-Skip Group, 'micro-instruction encoding' permits multiple instructions in one word.

r: A=0 / B=1 register
i: Direct=0 / Indirect=1 addressing
p: Zero=0 / Current=1 page
f: Hold=0 / Clear=1 device flag
s: bit of I/O device select code
m: bit of memory address
e: 1 to enable rotate or shift micro-instruction
.: 1 to enable additional micro-instruction
_: doesn't matter

HP 21xx Series Instruction Set

Opcode    Bit Encoding                Description
------    ---------------------       -------------------------------------------------------
Shift-Rotate Group:
NOP       0 000 000 000 000 000       No operation

CLE       0 000 .0. ... 1.. ...       0 --> E
SLr       0 000 r0. ... ..1 ...       Skip if LSB of A or B = 0

rLS       0 000 r0e 000 .e. 000       Arithmetic Shift Left A or B
rRS       0 000 r0e 001 .e. 001       Arithmetic Shift Right A or B

RrL       0 000 r0e 010 .e. 010       Rotate A or B Left
RrR       0 000 r0e 011 .e. 011       Rotate A or B Right

rLR       0 000 r0e 100 .e. 100       Shift A or B Left, 0 --> sign

ERr       0 000 r0e 101 .e. 101       Rotate A or B Right with E
ELr       0 000 r0e 110 .e. 110       Rotate A or B Left  with E

rLF       0 000 r0e 111 .e. 111       Rotate A or B Left Four
Alter-Skip Group:
CLr       0 000 r10 1.. ... ...       0        --> A/B
CMr       0 000 r11 0.. ... ...       NOT(A/B) --> A/B   (one's CoMplement A)
CCr       0 000 r11 1.. ... ...       -1       --> A/B   (Clear and Complement A)

CLE       0 000 .1. .01 ... ...       0      --> E
CME       0 000 .1. .10 ... ...       NOT(E) --> E
CCE       0 000 .1. .11 ... ...       1      --> E

SSr       0 000 r1. ... .1. ...       Skip if Sign of A/B = 0
SLr       0 000 r1. ... ..1 ...       Skip if LSB  of A/B = 0
SZr       0 000 r1. ... ... .1.       Skip if         A/B = 0
SEZ       0 000 .1. ... 1.. ...       Skip if        E = 0

INr       0 000 r1. ... ... 1..       A/B + 1 --> A/B, if signed overflow set OVF, if carry 15 set E

RSS       0 000 .1. ... ... .01       Reverse Skip Sense
Input/Output Group:
HLT       1 000 _1f 000 sss sss       Halt

STF       1 000 _10 001 sss sss       1 --> device flag 
CLF       1 000 _11 001 sss sss       0 --> device flag
SFC       1 000 _10 010 sss sss       Skip if device flag = 0 (device busy)
SFS       1 000 _10 011 sss sss       Skip if device flag = 1 (device ready)

MIr       1 000 r1f 100 sss sss       device buffer OR A/B --> A/B  (Merge Into A or B)
LIr       1 000 r1f 101 sss sss       device buffer --> A/B         (Load Into A or B)
OTr       1 000 r1f 110 sss sss       A/B --> device buffer         (OuTput A or B)

STC       1 000 01f 111 sss sss       1 --> device control bit
CLC       1 000 11f 111 sss sss       0 --> device control bit

STO       1 000 010 001 000 001       1 --> overflow
CLO       1 000 011 001 000 001       0 --> overflow
SOS       1 000 01f 011 000 001       Skip if overflow = 1
SOC       1 000 01f 010 000 001       Skip if overflow = 0
Memory Reference Group:
LDr       i 110 rpm mmm mmm mmm       (M) --> A/B   (Load A or B)

STr       i 111 rpm mmm mmm mmm       A/B --> (M)   (Store A or B)

ADr       i 100 rpm mmm mmm mmm       A/B + (M) --> A/B, if signed overflow set OVF, if carry 15 set E

CPr       i 101 rpm mmm mmm mmm       Skip if A/B <> (M)   (ComPare to A or B)

AND       i 001 0pm mmm mmm mmm       A AND (M) --> A
XOR       i 010 0pm mmm mmm mmm       A XOR (M) --> A
IOR       i 011 0pm mmm mmm mmm       A  OR (M) --> A

ISZ       i 011 1pm mmm mmm mmm       (M) + 1 --> (M), skip if (M) = 0

JMP       i 010 1pm mmm mmm mmm       Jump: M --> P
JSB       i 001 1pm mmm mmm mmm       Jump to SuBroutine: P+1 --> (M),  M+1 --> P
Some Useful Micro-instruction Sequences:
CLr,INr                               1 --> r

CMr,INr                               -r --> r   (take negative of A or B)

CMr                                   r - 1 --> r  (decrement A or B)

SZr                                   skip if r =  0
SZr,RSS                               skip if r <> 0
SSr                                   skip if r <  0
SSr,RSS                               skip if r >= 0
SSr,SZr                               skip if r <= 0
SSr,SZr,RSS                           skip if r >  0

Micro-instruction Notes:

Table 1:
Permitted Shift-Rotate combinations

(executed left to right)

Table 2:
Permitted Alter-Skip combinations

(executed left to right)

  1. Permitted sequences of micro-instructions are shown in tables 1 and 2. Only one micro-instruction can be chosen from a multiple choice column.

  2. Shift-Rotate instructions have two possible shift-rotations.
    A "1" in bit 9 enables shifts or rotates in the first position,
    a "1" in bit 4 enables shifts or rotates in the second position.

  3. In the Alter-Skip group, if two or more skip functions are combined, the skip will occur if either or both conditions are met. One exception exists: refer to RSS instruction.

  4. RSS Instruction: Skip occurs for any of the preceding skip instructions, if present, when the non-zero condition is met. RSS without a skip instruction in the word causes an unconditional skip. If a word with RSS also includes both SSA/B and SLA/B bits 15 and 0 must both be one for skip to occur. In all other cases the skip occurs if one or more skip condition is met.

  5. Note CLE, SLA and SLB instructions have encodings in both the Shift-Rotate group and Alter-Skip group.

  6. (Bit 11 of SLA instruction in Alter-Skip group appears to be incorrect in source documentation!!)

Miscellaneous Notes:

  1. The A and B registers may be addressed as locations 00000 and 00001 respectively.

  2. ISZ referencing locations 0 or 1 (A or B register) does not cause setting of the extend or overflow bits (unlike INA and INB).

  3. When applicable, the extend (E) bit is set upon carry from bit 15 (2^15). The overflow bit is set if an applicable operation results in overflow of the two's complement (signed) interpretation of the result, i.e.: if the sign bit is altered such that it no longer correctly represents the result.

  4. The extend bit is not affected unless specifically stated. However, if a rotate-with-E instruction (ERA/B, ELA/B) is coded but disabled by a "0" in bit 9 or 4, the E register will be updated even though the A or B register is not affected; code a NOP (three zeros) to avoid this situation.

  5. I/O Instructions: Bit 11, where relevant, specifies the A- or B-register or distinguishes between set control and clear control; otherwise it may be "1" or "0" without affecting the instruction (although the assembler will assign zeros, as shown).

(Compiled from HP-2100A Reference Manual from http://oscar.taurus.com/~jeff/2100/index.html)


Prioritised vectored interrupt servicing is a standard provision of the processors. The interrupt vector address for a channel is the same as the channel select code. To handle an interrupt the appropriate interrupt vector memory location must be loaded with an instruction (not the address of the interrupt service routine). For example, to handle an interrupt for channel 11, memory location 11 must be loaded with an instruction. When an interrupt occurs the instruction will be executed without first altering or loading the PC. Consequently, if the instruction is a JSB to an interrupt service subroutine then the return address placed in the first word of the subroutine will be the PC value when the interrupt occurred (in other words: the desired restart address).

Once the processor has trapped thru an interrupt vector it is deemed to be executing at the associated priority level and remains so until the flag bit (or control bit?) for the interrupting channel is cleared. Thus, the last thing a typical interrupt service subroutine does is to clear the channel flag and return from the subroutine.

Lower priority interrupts (channels with higher select code) cannot interrupt the processor when it is executing at a higher priority level (interrupted by a channel with lower select code).

Reserved Channels and Memory Locations

A few channels and memory locations have dedicated applications, independant of the I/O bus interface slots. These are documented in the table below.

For DMA, memory protection and parity the applicable optional board(s) must be installed.

Reserved Channels and Memory Locations
Input/Output Use Output
Control Bit Flag Bit Channel / Address Memory Location
global device &
interrupt control
  clear all controls [1]interrupts enable 00 A register
front panel
& overflow
S-register (front panel lamps) [6]front panel switches / S-register [6] overflow 01 B register
DMA Channel 1
control [3]
address / lengthlengthselect address or lengthDMA complete 02 A/B exit, mem protect lower bound
DMA Channel 2
control [3]
address / lengthlengthselect address or lengthDMA complete 03 A/B exit
last interrupt address [2]   04 power fail interrupt
memory protection
& errors [5]
protect upper bounderror type/addrprotection interrupt enableparity interrupt enable 05 memory error interrupt
DMA Channel 1 [4]device startabort 06 DMA 1 interrupt
DMA Channel 2 [4]device startabort 07 DMA 2 interrupt
I/O interface
(slot 203 on 2116)
as per interfaceas per interface as per interfaceas per interface 10 corresponding I/O interrupt

. . .

"" ""

. . .

I/O interface
(slot 218 on 2116)
"""" 27 corresponding I/O interrupt


  1. Clearing control bit on channel 0 clears the control bit of all devices from 6 up.

  2. Address/channel select code of most recent interrupt. [ref: 2116B Class Vol. 2 / pg. 6-38]

  3. DMA Control.
    Control bit selects the Address register (0) or Length register (1).
    Address register: input operation (bit 15=0) or output operation (bit 15=1) and starting address of transfer (bits 14:0).
    Length register: negative of length (word count) of transfer (bits 13:0, bits 15 and 14 read as 0). The program loads the length register with the negative of the write count or negative of the maximum read count before the operation. The DMA hardware increments the register towards 0 during the operation. Upon completion of the operation the program can use the value read from the length register to calculate the number of words transferred.

  4. DMA Control.
    Device & options register: STC per word (bit 15), CLC at end (bit 13) and device select-code (bits 5:0). With bit 15 set, an STC operation is performed on the device interface for every word transfer. With bit 13 set, a CLC operation is performed on the device interface at the completion of the operation.

    [DMA refs: 2100 documention, example program in Type 13181 Magnetic Tape I/O Interface manual, experimentation with the hardware]

  5. Memory Protect and Memory Parity information is from 2100 documention, presumed applicable to 2116.

  6. On the 2115/6 it is only possible to read the front panel switches. On the 2100s, an actual register (the S-register) exists which can be altered by the front panel switches or an output instruction, can be read by an input instruction, and is displayed on the front panel lamps. Not sure about the 2114.

  7. Two sequential select-codes apply to one physical slot for use by some devices. [ref: 2116B Class Vol. 2 / pg. 6-1]

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HP 21xx Series
Jun 2004