The JMOS Family of Integrated Circuits

Many calculators of Japanese origin from the late 1960s utilized integrated circuits from a family of ICs particular to several Japanese companies. Each of the manufacturers contributed a series with their own part numbers to the family but all are based on the same technology. In some cases the same IC was produced by more than one manufacturer but with different part numbers. Sometimes ICs from two or more of the series may be found in one calculator.

NEC and Hitachi seem to have gone through several revisions of their series, making improvements along the way.

Organisationally this is analogous to the situation in North America where manufacturers such as Fairchild, TI, National Semiconductor, etc. all produced series of TTL ICs which comprised a standard TTL family, although the manufacturers eventually converged on the common 7400 part numbers.

In the absence of any other name, "JMOS" has been chosen as a name for this family, for Japanese MOS.

Some of the ICs in this family, such as the TM4105 64-bit shift register, are (for the period and market) high density. Calculators built using this family ended up embodying two ends of the spectrum of technology: at one end utilising such high density devices; at the other, most of the gates in the calculators were still constructed from discrete diodes and resistors.
Members of Family: NEC µPD1 Series
NEC µPD10/100 Series
Toshiba TM4000 Series
Hitachi HD700 Series
Hitachi HD3100 Series
Philco SC1772
Period: Late 1960s.
Technology: Several factors indicate this family is MOS technology:
  • the presence of relatively high density devices,
  • high supply voltage,
  • high resistance load resistors in the range 30K to 200K suggest the internal transistors are voltage sensing (such as MOS) rather than current sensing (such as bipolar),
  • the µPD7 and µPD101C have functionality indicative of MOS transistors,
  • a board was found with silk-screened references to VG and VD.
Supply Voltage: -24V. A few devices require an additional -14V supply.
Logic: Gate symbols are presented in accordance with
  • TRUE = 0V
  • FALSE = -24V
Most outputs are open-collector, closing to GND (TRUE) and requiring external pull-down resistors to -24V (FALSE).

Note though, that some calculators utilising these ICs are designed with negative logic, thereby reversing the above. AND and OR gate symbols should also be swapped.

Packaging: TO-100 (10-pin) and TO-101 (12-pin) cans and standard DIP, depending on the date of production and the manufacturer.
  • The flip-flops in this logic family are Master/Slave D-type flip-flops with the clocks for the master and slave sections kept separate.
    • C = Capture Input (Master section clock)
    • T = Toggle Input (Slave section clock)
    The state of the D input is captured when C is FALSE (-24V). The Q output is set in accordance with the captured state when T goes to FALSE. See the comments on Japanese clocking scheme.

  JMOS Family
Calculators | Integrated Circuits | Displays | Simulations
2000 Aug