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These I/O interfaces provide for communication over an asynchronous serial RS-232 or 20mA current loop link. Serial/parallel conversion is provided in hardware.
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The 12531A is not included here as it is a very different board.
The "High Speed Terminal" name for the 12531D is relative to the era: the provided jumper positions permit operation up to only 2400 BPS. It can function up to 19,200 BPS by jumpering to the other outputs of the clock divider IC (the U42-x entries in the table).
These boards are not double-buffered and there are some resultant timing constraints for software to deal with.
Of particular note driver software may have difficulty dealing with reception of characters with only 1 stop bit.
This is a consequence of the design of the board in that reception of a character is not completed or indicated to the program (setting of the channel flag) until the end of the first stop bit, at which point the following start bit has already begun.
The design of the board is such that the flag bit must be clear at/near the beginning of the start bit for the board clock to synchronize properly on the character.
To work successfully with 1 stop bit the program must clear the flag within a very short window after the flag has been set. With 2 stop bits the program has the entire period of the second stop bit to work with.
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12531BCD
CTµL | 2116 | I/O Interfaces | Programming Ref | Software | 2116C Refurb HP 21xx Series |
bhilpert Jun 2004 |