HP 9830 - Machine Reference

Memory Cycle State Machine Sequences
Inputs Out to 1103 Outputs State FF State FF Inputs ------- ---- ----------- ----- ----------- ------- --- --------------- ----------------- Cycle MCC MCB MCA MCP Type Step RDM WTM REF State nCE nPC RnW MAC TPC MEN MCC MCB MCA MCP J K J K J K D ======= ==== === === === ===== === === === === === === === === === === = = = = = = = Idle 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 1 Read 1 1 0 0 5 1 1 1 0 0 1 0 1 0 1 1 0 0 0 0 0 1 2 1 0 0 13 1 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 3 1 0 0 12 1 1 1 0 0 1 1 1 0 0 0 0 0 1 0 0 0 4 1 0 0 8 1 1 1 0 0 1 1 0 0 0 0 1 0 1 0 0 1 5 1 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 0 0 0 0 1 6 1 0 0 9 1 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 7 1 0 0 11 0 1 1 1 0 1 1 0 1 1 1 0 0 0 1 0 0 8 1 0 0 10 0 1 1 1 0 1 1 0 1 0 0 0 1 1 0 0 0 9 1 0 0 14 0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 0 EOC 10 1 0 0 2 0 1 1 1 0 1 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 1 1 0 1 1 ------- ---- ----------- ----- ----------- ------- --- --------------- ----------------- Idle 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 1 Write 1 0 1 0 5 1 1 1 0 0 1 0 1 0 1 1 0 0 0 0 0 1 2 0 1 0 13 1 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 3 0 1 0 12 1 1 1 0 0 1 1 1 0 0 0 0 0 1 0 0 0 4 0 1 0 8 1 1 1 0 0 1 1 0 0 0 0 1 0 1 0 0 1 5 0 1 0 1 1 0 1 1 0 1 0 0 0 1 1 1 0 0 0 0 1 6 0 1 0 9 1 0 1 1 0 1 1 0 0 1 1 1 0 0 1 0 1 7 0 1 0 3 0 1 1 1 0 1 0 0 1 1 1 0 0 0 0 0 1 8 0 1 0 11 0 1 1 1 0 1 1 0 1 1 1 0 0 0 1 0 0 9 0 1 0 10 0 1 1 1 0 1 1 0 1 0 0 0 1 1 0 0 0 10 0 1 0 14 0 1 0 1 1 1 1 1 1 0 0 1 1 1 0 0 0 EOC 11 0 1 0 2 0 1 1 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 1 0 0 0 0 0 1 1 1 0 1 1 ------- ---- ----------- ----- ----------- ------- --- --------------- ----------------- Idle 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 1 Refresh *0 0 0 1 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 0 1 1 cycle 0 1 0 0 1 1 1 0 1 1 0 1 0 0 0 1 1 0 0 0 0 0 1 2 0 0 1 9 1 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 3 0 0 1 11 0 1 1 1 0 1 1 0 1 1 1 0 0 0 1 0 0 4 0 0 1 10 0 1 1 1 0 1 1 0 1 0 0 0 0 1 0 1 0 5 0 0 1 8 1 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 1 cycle 1 1 0 0 1 1 1 0 1 1 0 1 0 0 0 1 1 0 0 0 0 0 1 2 0 0 1 9 1 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 3 0 0 1 11 0 1 1 1 0 1 1 0 1 1 1 0 0 0 1 0 0 4 0 0 1 10 0 1 1 1 0 1 1 0 1 0 0 0 0 1 0 1 0 5 0 0 1 8 1 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 1 cycle 2 1 0 0 1 1 1 0 1 1 0 1 0 0 0 1 1 0 0 0 0 0 1 2 0 0 1 9 1 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 etc. 3 0 0 1 11 0 1 1 1 0 1 1 0 1 1 1 0 0 0 1 0 0

Memory Cycle State Machine Sequences

                  Inputs             Out to 1103   Outputs            State FF         State FF Inputs
-------  ----   -----------  -----   -----------   -------   ---   ---------------    -----------------
 Cycle                                                                                MCC  MCB  MCA MCP
 Type    Step   RDM WTM REF  State   nCE nPC RnW   MAC TPC   MEN   MCC MCB MCA MCP    J K  J K  J K  D
=======  ====   === === ===  =====   === === ===   === ===   ===   === === === ===    = =  = =  = =  =
 Idle      0     0   0   0      0     1   1   1     0   0     0     0   0   0   0     0 1  1 1  0 1  1
 Read      1     1   0   0      5     1   1   1     0   0     1     0   1   0   1     1 0  0 0  0 0  1
           2     1   0   0     13     1   1   1     0   0     1     1   1   0   1     1 0  0 0  0 0  0
           3     1   0   0     12     1   1   1     0   0     1     1   1   0   0     0 0  0 1  0 0  0
           4     1   0   0      8     1   1   1     0   0     1     1   0   0   0     0 1  0 1  0 0  1
           5     1   0   0      1     1   0   1     1   0     1     0   0   0   1     1 0  0 0  0 0  1
           6     1   0   0      9     1   0   1     1   0     1     1   0   0   1     1 0  0 0  1 0  1
           7     1   0   0     11     0   1   1     1   0     1     1   0   1   1     1 0  0 0  1 0  0
           8     1   0   0     10     0   1   1     1   0     1     1   0   1   0     0 0  1 1  0 0  0
           9     1   0   0     14     0   1   1     1   1     1     1   1   1   0     0 1  1 1  0 0  0
  EOC     10     1   0   0      2     0   1   1     1   0     1     0   0   1   0     0 0  0 1  0 1  0
                 1   0   0      0     1   1   1     0   0     1     0   0   0   0     0 1  1 1  0 1  1
-------  ----   -----------  -----   -----------   -------   ---   ---------------    -----------------
 Idle      0     0   0   0      0     1   1   1     0   0     0     0   0   0   0     0 1  1 1  0 1  1
 Write     1     0   1   0      5     1   1   1     0   0     1     0   1   0   1     1 0  0 0  0 0  1
           2     0   1   0     13     1   1   1     0   0     1     1   1   0   1     1 0  0 0  0 0  0
           3     0   1   0     12     1   1   1     0   0     1     1   1   0   0     0 0  0 1  0 0  0
           4     0   1   0      8     1   1   1     0   0     1     1   0   0   0     0 1  0 1  0 0  1
           5     0   1   0      1     1   0   1     1   0     1     0   0   0   1     1 1  0 0  0 0  1
           6     0   1   0      9     1   0   1     1   0     1     1   0   0   1     1 1  0 0  1 0  1
           7     0   1   0      3     0   1   1     1   0     1     0   0   1   1     1 0  0 0  0 0  1
           8     0   1   0     11     0   1   1     1   0     1     1   0   1   1     1 0  0 0  1 0  0
           9     0   1   0     10     0   1   1     1   0     1     1   0   1   0     0 0  1 1  0 0  0
          10     0   1   0     14     0   1   0     1   1     1     1   1   1   0     0 1  1 1  0 0  0
  EOC     11     0   1   0      2     0   1   1     1   0     1     0   0   1   0     0 0  0 1  0 1  0
                 0   1   0      0     1   1   1     0   0     1     0   0   0   0     0 1  1 1  0 1  1
-------  ----   -----------  -----   -----------   -------   ---   ---------------    -----------------
 Idle      0     0   0   0      0     1   1   1     0   0     0     0   0   0   0     0 1  1 1  0 1  1
Refresh   *0     0   0   1      0     1   1   1     0   0     1     0   0   0   0     0 1  0 1  0 1  1
cycle 0    1     0   0   1      1     1   0   1     1   0     1     0   0   0   1     1 0  0 0  0 0  1
           2     0   0   1      9     1   0   1     1   0     1     1   0   0   1     1 0  0 0  1 0  1
           3     0   0   1     11     0   1   1     1   0     1     1   0   1   1     1 0  0 0  1 0  0
           4     0   0   1     10     0   1   1     1   0     1     1   0   1   0     0 0  0 1  0 1  0
           5     0   0   1      8     1   1   1     0   0     1     1   0   0   0     0 1  0 1  0 1  1
cycle 1    1     0   0   1      1     1   0   1     1   0     1     0   0   0   1     1 0  0 0  0 0  1
           2     0   0   1      9     1   0   1     1   0     1     1   0   0   1     1 0  0 0  1 0  1
           3     0   0   1     11     0   1   1     1   0     1     1   0   1   1     1 0  0 0  1 0  0
           4     0   0   1     10     0   1   1     1   0     1     1   0   1   0     0 0  0 1  0 1  0
           5     0   0   1      8     1   1   1     0   0     1     1   0   0   0     0 1  0 1  0 1  1
cycle 2    1     0   0   1      1     1   0   1     1   0     1     0   0   0   1     1 0  0 0  0 0  1
           2     0   0   1      9     1   0   1     1   0     1     1   0   0   1     1 0  0 0  1 0  1
  etc.     3     0   0   1     11     0   1   1     1   0     1     1   0   1   1     1 0  0 0  1 0  0

This is the output of a spreadsheet simulation of the memory cycle state machine.

The idle state and the state sequences for the read, write and refresh cycles are listed. Each line is one state, except for an extra line around the beginning of the refresh sequence to show how the REF signal preconditions the JK FF inputs before the first transition out of the 0 state. State transitions are triggered by MCK so each state is one MCK cycle long.

The four 1-bit state variables have been arbitrarily composed into a state number as MCC.MCB.MCA.MCP. The logic design seems a little ad-hoc, one observation is that - for the most part, but not entirely - the state sequence is a gray-code with only 1 of the 4 bits changing at each transition.

Some other points of note:

One can see the 1103 precharge being enabled before the chip-enable.
The solitary write pulse on the R/nW line in the write sequence.
The T-register parallel-load pulse on the TPC line. While this clock pulse shows up in both the read and write sequences, the parallel load is only enabled (TMC) during a read.
How the refresh sequence loops instead of returning to the 0 state. The negative edge of MCC increments the refresh row counter so each sub-cycle refreshes a different row.