The AL-1000 is a digit-serial decimal number processor controlled by a hardwired state machine and driving a multiplexed display. The digits of decimal numbers are processed in serial, with each 4-bit BCD digit being processed in parallel. Primary data paths are 4-bits wide. The control state machine is quite well defined, which assisted greatly in making it amenable to reverse engineering.
Figure 1 is a block diagram of the AL-1000. Following this are brief descriptions of the various elements.
The names for flip-flop elements are taken from the labeling on the printed circuit boards. Some of the names are non-alphabetic symbols on the PCBs and have been renamed, such as "÷" with "FDIV". Most of the names are a readily apparent abbreviation of their purpose. A few, such as the "T" flip-flops have remained ciphers as to the source or meaning of their name, although their purpose has been decoded. Names for unlabeled elements and signals have been created as seemed appropriate.
|Figure 1: Casio AL-1000 Calculator Architecture|
|Table 1: Brief Descriptions of Principle Elements|
|Section||Element||Purpose / Use|
|Timing||PG astable||The master clock astable flip-flop.|
|SG flag||Toggles the activity of the G and S counters, to select between number cycles and state transitions.|
|G counter||A 3-stage ring counter to produce clock signals for core memory read/write cycles.|
|S counter||A 3-stage (6-state) Johnson counter to produce clock signals for state machine transitions.|
|Keyboard||KN Numeral encoder||Encodes the numeral keys into BCD format.|
|KF Function encoder||Encodes the function keys into a 4-bit code.|
|KR Rounding encoder||Encodes the position of the rounding switch into BCD format.|
|T State Machine||A small state machine to sequence between display, numeral entry, function execution, and program execution.|
|TAB, TCD latches||2-bit master/slave latch to hold the state.|
|ST Stop flag||Controls reloading of the T state with the fetch code during program execution.|
|Function Selection||U latch||4-bit latch to hold the code of the function being executed.|
|FMUL, FDIV flags||Indicate that the next add or subtract completes a multiply or divide.|
|F54 flag||Flag to take the function execution state machine through the rounding procedure.|
|FNEG flag||Indicates whether the displayed number is negative.|
|The main state machine to sequence execution of addition, subtraction, multiplication, etc.|
|R, L latches||5-bit master/slave latch to hold the state. The L latch determines the current state.|
|Other Flags||FN flag||During number entry, flag indicating whether a new number or within a number.|
|FDP flag||Indicates that the decimal point has been pressed during number entry.|
|GAM flag||(Gamma) Captures data states within a number cycle.|
|BET flag||(Beta) Used for some miscellaneous purposes during function execution.|
|W0 flag||Captures the zero-state of the most recent digit data from the arithmetic unit (W=0).|
|PC flag||Indicates the completion of program execution.|
|Register Selection||Q flag||Selects between the X or Y operand registers.|
|PA flag||Selects between number registers and program storage.|
|PB flag||Selects between program 1 storage and program 2 storage.|
|Data Handling||A, B latches||Two 4-bit latches to hold digit data from the memory and keyboard, and which feed the arithmetic unit.|
|GR flag||Selects between the A or B latch being loaded with data from core memory.|
|Arithmetic Unit||A 4-bit BCD parallel adder with decimal sum correction.|
|C flag||Tens Carry Flag.|
|D Display latch||A 4-bit latch to hold the multiplexed digit being displayed.|
|Other||DP Decimal Point counter||A base-16 counter to identify the current position of the decimal point in the display, and for use as a loop counter during multiply, divide and square root.|
|DGT Digit counter||A base-16 counter to select the digit in a register. Constructed from a 4-stage Johnson counter and fifth binary bit.|
|Core Memory Arrays||4 bit-arrays of 8 by 14 cores each, for number register and program storage.|
From a user perspective, the calculator provides two operand registers, 4 memory registers and 30 locations of program storage. These are all stored in a small core memory.
The two operand registers (X and Y) and two of the memory registers (M1 and M2) are each 14 numeric digits, a sign digit and a digit to hold the decimal point position. The other two memory registers (M3 and M4) are 7 numeric digits and a decimal point position each (no sign). The contents of the X register appear in the Nixie tube display, the Y Register is the '2nd operand'.
The program storage is comprised of the equivalent of another two full registers. The numeric and sign digits are the instruction storage locations. The decimal point position digit is used as the program counter during program execution. The PB flag is used to select between the two sets of instruction storage. The program storage can be utilised either as two programs of up to 15 instructions each or as 1 program of up to 30 instructions.
The functional layout of memory is shown in table 2a. It might seem sensible to implement this in core as 4 bit-arrays of 16 by 8 or 16 by 7. However, the designers chose another layout: 4 arrays of 14 by 8, as shown in table 2b. Each 16-digit register occupies two 8-digit columns. This probably simplified the address decoding logic slightly as there are no wasted cores, nor is special logic needed for the absent upper digits of M3 and M4. The ordering of registers in columns is muddled, perhaps for the sake of more direct PCB traces, as it doesn't matter as far as operation goes.
All digits are 4-bits, numeric digits of numbers are encoded in BCD (1248) format, the decimal point position and program counter digits are base-16. Program instructions are also base-16, using the same coding as that which the function keys are encoded into for storage in the U latch, as presented in table 2c. Programs are entered by using the numeric keys to enter the appropriate code for a function. For code values greater than 9 the decimal point is pressed to turn on the '8' bit. Code 13 (or '5.') is used internally during the square root procedure and is not intended for use by the user.
|Table 2c: Program Instruction Codes|
|(Square Root part 2)||13||5.|
|Stop (data entry)||14||6.|
The various elements are distributed amongst the printed circuit boards as follows:
|Table 3: Physical Board Contents|
|1||D Latch, BCD-to-decimal decoder and drivers, digit drivers, Nixie display tubes|
|2||Keyboard encoders, ST flag, DP Counter and decoders, Power-On-Reset circuitry|
|3||MAIN1||Function latch (U) and decoding, FMUL,FDIV,F54,FNEG,FN,FDP flags|
|4||MAIN2||Function execution state sequencing, BET,GAM flags|
|5||MAIN3||Function execution state latches (R&L) and decoders|
|6||SUB||Master clock (PG), G and S counters, SG and GR flags, T state machine, h monostable|
|7||ADDER||A & B latches, arithmetic unit, C flag|
|8||ADDRESS||Digit counter and decoders, Q,PA,PB,PC flags, register addressing decoders|
|9||DRIVE||Core memory address line drivers|
|10||Core memory planar array, inhibit drivers, sense amplifiers, W0 flag|
T States |
Casio AL-1000 Technical Description