EarlyElectronicCalculator Casio AL-1000 Calculator Technical Description:Timing

### 1. The Digit Clock and the Number Cycle

The master clock is the astable flip-flop PG. PG selectively drives two counters, the G counter and the S counter. Most of the time the G counter is active and the S counter inactive. The G counter is a 3-stage ring counter and produces signals to control the core memory read/write cycles. One 3-state cycle of the G counter is one digit read/write cycle. The S counter is discussed below.

The G counter also clocks the 16-state digit counter. The outputs from this counter are used to address digits in the core memory and to define a number cycle (one 16-stage scan of a register) via the decoded signals DGTn. The DGT counter is bi-directional so numbers can be processed either from MSD to LSD or from LSD to MSD.

 Figure 1: Digit Timing and the Number Cycle

### 2. The Display Cycle

When the calculator is simply displaying, the digit counter counts down on the negative edge of each G2 pulse. At the same time the A latch is cleared. At G1 sense pulses from core set the according bits in the A latch, so loading the digit data into the A latch. The digit data is transferred to the D latch when the A latch is cleared at the end of the digit period, so there is a one-digit-time stagger between the data in the A latch and the data displayed.

The DP counter is loaded with the decimal point position of the X register each time digit 1 from the register passes through the A latch. During the rest of the number cycle, the DP counter is incremented for each digit. When it cycles around to 0, the decimal point is turned on. For example, if the number has 3 decimal positions, digit 1 of the X register will contain 3 and this will be loaded into the DP counter at time DGT1. As the digit counter counts down and digits are displayed from the MSD down, the DP counter counts up. 16-3=13 digit periods later the DP counter hits 0 and the decimal point is turned on for that digit period.

### 3. The State Clock and State Transitions

The S counter produces signals to guide the transitions of the function-execution state machine as well as the T state machine. The S counter is a 3 stage Johnson counter producing a sequence of 6 edges for triggerring various actions. Only one of the S and G counters is active at a given time, as selected by the SG flip-flop.

When an operation is requested or active the SG flip-flop will be set to 1 at the beginning of each number cycle. This disables the G counter and enables the S counter for one (6-stage) cycle. During the S counter cycle, state machine transitions occur. As the S counter cycle ends the SG flip-flop is reset, disabling the S counter and re-enabling the G counter and so starting another number cycle. State machine transitions are thus interjected between number cycles.

Figure 3 shows the events for a (hypothetical) 2-state function execution. The process is initiated when a function key is pressed, producing KFP (Keyboard Function Press). KFP triggers the h monostable to start a debounce interval. When h falls back to 0, TA and TB are loaded with the T state-machine code for function execution. TA or TB now being non-zero, TSREQUEST goes 1 and at the next DGT1 the SG flag is set to 1, starting an S counter cycle. During the S counter cycle, the state of TA and TB are transferred to TC and TD. TC and TD are decoded to produce TSFCT. The T state machine is now in the function execution state.

 Figure 3: State-Clock Cycles and State Cycles

The encoded function code for the pressed key is also latched into the U latch. The code in U persists for the duration of the function execution.

The state of the function execution state machine is stored in the 5-bit R & L latches. The contents of the L latch defines the current state, the R latch is a master or priming latch for the L latch. U being non-zero results in a new non-zero state being set up at the inputs to the R latch via the sequencing logic. This is latched in and transferred a moment later to the L latch to become the current state, which persists for the upcoming number cycle.

At the end of the number cycle, another S cycle is enabled. The sequencing logic presents the next state to the R latch, which is latched in, then transferred to the L latch. The next number cycle then proceeds under the direction of the new state.

A little trick is played with the transferring of data from the R to the L latch to permit states to loop on themselves without requiring dedicated sequencing gates. The L latch is only reset and loaded if a new, non-zero, state has been loaded into the R latch by the sequencing logic. If not, the L latch remains the same, resulting in a loop of the current state. At the end of a function, when it is really desired to load the L latch with 0 (to return to the idle state) the TEND pulse resets the L latch directly.

 Architecture | Electronics | Arithmetic | Timing | T States | States | Procedures | Numeral-Entry Casio AL-1000 Technical Description EEC bhilpertNov 2004